Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-11-30
2002-12-03
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S566000, C365S230030
Reexamination Certificate
active
06489837
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an input/output circuit for an integrated circuit. More specifically, the present invention relates to a controlled impedance for an input/output circuit of an integrated circuit.
RELATED ART
Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), typically include input/output blocks (IOBs) for providing and receiving external data. An IOB will therefore include an output driver circuit.
FIG. 1
is a block diagram of a conventional output driver circuit
100
, which includes an input terminal
101
, an output terminal
102
, p-channel transistors
103
1
-
103
N
, n-channel transistors
1041
-
104
N
and I/O pad
105
. Input terminal
101
is coupled to the gates of transistors
103
1
-
103
N
and to the gates of transistors
1041
-
104
N
. The source terminals of p-channel transistors
103
1
-
103
N
are coupled to a V
CC
supply voltage terminal, and the source terminals of n-channel transistors
104
1
-
104
N
are coupled to a ground terminal. The drain terminals of transistors
103
1
-
103
N
and
104
1
-
104
N
are coupled to I/O pad
105
through output terminal
102
.
When a logic low signal is applied to input terminal
101
, p-channel transistors
103
1
-
103
N
are all turned on, thereby coupling I/O pad
105
to the V
CC
supply voltage terminal. In this condition, driver circuit
100
presents a predetermined resistance to I/O pad
105
. This resistance is determined by the on-resistances of transistors
103
1
-
103
N
, taken in parallel.
Similarly, when a logic high signal is applied to input terminal
101
, n-channel transistors
104
1
-
104
N
are all turned on, thereby coupling I/O pad
105
to the ground terminal. In this condition, driver circuit
100
presents a predetermined resistance to I/O pad
105
. This resistance is determined by the on-resistances of transistors
104
1
-
104
N
, taken in parallel.
In certain circumstances, it is desirable for the resistance presented to I/O pad
105
to have a predetermined relationship with an external resistance coupled to I/O pad
105
. For example, it may be desirable for the resistance presented to I/O pad
105
to match an impedance of a trace or wire coupled to I/O pad
105
to improve signal integrity.
Unfortunately, the resistance presented by output driver circuit
100
is fixed at a predetermined value, thereby preventing the driver circuit from being optimized for different trace or wire impedances. Thus, the operating flexibility of driver circuit
100
is limited. In addition, the predetermined resistance value of output driver circuit
100
will vary in response to temperature, voltage and/or process variations. Thus, even if the predetermined resistance of output driver circuit
100
initially has a desirable relationship with a trace or wire impedance coupled to I/O pad
105
, this relationship may shift as the resistance of output driver circuit
100
changes in response to changes in temperature, voltage or process.
It would therefore be desirable to have an output driver circuit which overcomes the deficiencies of the above described driver circuit
100
.
SUMMARY
Accordingly, the present invention provides a system for controlling the impedances of output driver circuits on an integrated circuit chip. At least one output driver circuit is selected to operate as a p-channel reference circuit, and at least one output driver circuit is selected to operate as an n-channel reference circuit. Other output driver circuits are selected to operate as active output driver circuits and/or line termination circuits.
In one embodiment, the p-channel reference circuit includes a first set of p-channel transistors coupled in parallel between a V
CC
supply terminal and a first pad, and a p-channel reference resistor R
PREF
coupled between the first pad and a ground supply terminal. A control circuit determines which subset of transistors in the first set of p-channel transistors should be turned on to provide a pre-determined correspondence with the reference resistor R
PREF
. For example, the control circuit may determine which subset of transistors in the first set of p-channel transistors should be turned on to match the resistance of reference resistor R
PREF
. To make this determination, a first reference voltage generator provides a p-channel reference voltage V
PREF
to a first comparator. The first comparator compares the p-channel reference voltage V
PREF
with the voltage on the first pad. In response, the first comparator generates a control signal, which indicates whether the resistance of turned on transistors in the first set of p-channel transistors has a determined relationship with respect to the p-channel reference resistor R
PREF
and the p-channel reference voltage V
PREF
. The control circuit adjusts the subset of turned on p-channel transistors until the desired correspondence is provided.
The control circuit then addresses a selected group of one or more of the active output driver circuits, and transmits information identifying the determined subset of turned on p-channel transistors. This selected group of active output driver circuits will then turn on transistors corresponding to the determined subset of p-channel transistors to drive a logic high output signal, or provide a desired line termination.
In one embodiment, the control circuit dynamically updates the determined subset of p-channel transistors during operation of the chip, thereby compensating for variations in temperature, voltage and process.
In another embodiment, the first reference voltage generator is configured to provide a plurality of different p-channel reference voltages V
PREF
. The control circuit then determines different subsets of turned on p-channel transistors for each of the different p-channel reference voltages. The control circuit then addresses different groups of active output driver circuits, with each of the different groups being configured to enable different subsets of p-channel transistors, as determined by the control circuit.
In one embodiment, the first set of p-channel transistors includes fine adjustment p-channel transistors having the same resistance, and coarse adjustment p-channel transistors having binary weighted resistances.
The n-channel reference circuit is configured and controlled in a manner similar to p-channel reference circuit. More specifically, the n-channel reference circuit includes a first set of n-channel transistors coupled in parallel between a ground supply terminal and a second pad, and an n-channel reference resistor R
NREF
coupled between the second pad and the V
CC
supply terminal. A control circuit determines which subset of transistors in the first set of n-channel transistors should be turned on to provide a pre-determined correspondence with the reference resistor R
NREF
. To make this determination, a second reference voltage generator provides an n-channel reference voltage V
NREF
to a second comparator. The second comparator compares the n-channel reference voltage V
NREF
with the voltage on the second pad. In response, the second comparator generates a control signal, which indicates whether the resistance of turned on transistors in the first set of n-channel transistors has a determined relationship with respect to the n-channel reference resistor R
NREF
and the n-channel reference voltage V
NREF
. The control circuit adjusts the subset of turned on n-channel transistors until the desired correspondence is provided.
The control circuit then addresses a selected group of one or more of the active output driver circuits, and transmits information identifying the determined subset of turned on n-channel transistors. This selected group of active output driver circuits will then turn on transistors corresponding to the determined subset of n-channel transistors to drive a logic low output signal, or provide a desired line termination.
In general, the n-channel reference circuit can be controlled in the same manner as the p-channel reference circuit.
In a particular em
Bergendahl Jason R.
Hao Eunice Y. D.
Menon Suresh M.
Schultz David P.
Tan Jian
Chan H. C.
Hoffman E. Eric
Nuton My-Trang
Xilinx , Inc.
LandOfFree
Digitally controlled impedance for I/O of an integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digitally controlled impedance for I/O of an integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digitally controlled impedance for I/O of an integrated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2928956