Digitally controlled duty cycle integration

Details Digitally controlled duty cycle integration Digitally controlled duty cycle integration

1997-12-10

1999-08-10

Young, Brian

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

341144, H03M 166

Patent

active

059365650

ABSTRACT:
An inexpensive and reliable DCDCI (digitally controlled duty cycle integration) circuit and method for efficiently converting a digital input signal into a high resolution analog control voltage for use in a variety of closed-loop control systems and more particularly for use in synchronizers. In particular, this invention enables a microsynchronizer to cost-effectively align a clock signal locally generated by a VCXO to multiple incoming clock signals operating at various frequencies for synchronization with a transmitter. The microsynchronizer designed in accordance with this invention integrates APLL and DPLL circuits into a compact and cost-effective design by consolidating analog and digital phase error processing in a PEG (phase error generator) design. The PEG converts the phase error information into differential signals which are subsequently presented to an AC-DC converter for producing high resolution analog control voltages for the VCXO.

REFERENCES:
patent: 5712636 (1998-01-01), Buch
patent: 5764173 (1998-07-01), Flynn

Affiliated with

Also associated with

Rating

Digitally controlled duty cycle integration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digitally controlled duty cycle integration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digitally controlled duty cycle integration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1124370