Digitally controlled differential delay line circuit and method

Details Digitally controlled differential delay line circuit and method Digitally controlled differential delay line circuit and method

1998-10-21

2000-05-09

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Parallel controlled paths

327404, 327284, 327285, 327286, 327287, 327288, 327395, 327535, H03K 1762

Patent

active

060609397

ABSTRACT:
An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines. A reference voltage source is coupled to each of the delay elements and provides a reference voltage maintained at a substantially constant amplitude with respect to the power supply to each of the delay elements. The delayed signal may be a differential signal. Each of the delay elements may include one or more adjustable loads or adjustable current sources. An adjustable load may be implemented using P-FETs. In one embodiment, at least one of the delay elements of the first and second delay lines includes a plurality of selectable delay devices, each of which is associated with one of a plurality of selectable delay factors.

REFERENCES:
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C. J. Goetschel et al., "Programmable Delay Line," IBM Technical Disclosure Bulletin, 37:03 (1994).
R. Gopalan et al., "High-Speed Clock System Design with the ML6500 PACMan Programmable Adaptive Clock Manager," Application Note 21 of Micro Linear Corporation, pp. 1-16 (1993).
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