Digitally controlled delay circuit

Details Digitally controlled delay circuit Digitally controlled delay circuit

1987-04-29

1992-05-05

Callahan, Timothy P.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307606, 307263, 307451, H03K 513, G11C 1134

Patent

active

051110857

ABSTRACT:
A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.

REFERENCES:
patent: Re32515 (1987-10-01), Shoji
patent: 4209713 (1980-06-01), Satou et al.
patent: 4424456 (1984-01-01), Shiraki et al.
patent: 4620116 (1986-10-01), Ozawa
patent: 4638190 (1987-06-01), Hwang et al.
patent: 4658161 (1987-04-01), Spencer
patent: 4709170 (1987-11-01), Li
Ruoff, "Field Effect Transistor Clocked Logic", IBM Tech. Disclosure, vol. 8, No. 4, Sep. 1965, pp. 640-641.
Patent Abstracts of Japan, vol. 10, No. 213, Jul. 25, 1986.
IBM Technical Disclosure Bulletin, vol. 27, No. 12, May 12, 1985, "CMOS Delay Circuit", pp. 7134-7135.

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