Oscillators – With frequency adjusting means – With voltage sensitive capacitor
Reexamination Certificate
2002-05-03
2004-06-08
Nguyen, Minh (Department: 2816)
Oscillators
With frequency adjusting means
With voltage sensitive capacitor
C331S03600C, C331S1160FE, C455S197200
Reexamination Certificate
active
06747522
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of crystal oscillators. In particular, this invention is drawn to precise tuning control for crystal oscillators.
BACKGROUND OF THE INVENTION
Many communication systems require precise timing to permit synchronization of a receiver clock signal with a transmitter clock signal. Sophisticated communication algorithms require precise synchronization between the near and far end terminals for maximum data throughput on a communication channel.
The frequency of a crystal controlled oscillator tends to remain constant with a high degree of accuracy. However, even if substantially identical crystals with the same vibrational characteristics are used at the transmitter and receiver, temperature variations between the sites results in sufficient frequency mismatch between both ends of the communication channel to render the data unrecoverable. Further, process variation in the manufacture of the crystals typically results in mismatch on the same order of magnitude as that introduced by the temperature variations.
A frequency tracking system can be used to ensure synchronization between the ends of a communications channel. Voltage controlled crystal oscillators (VCXOs) are often used as components in a frequency tracking system. A common design incorporates varactor (voltage controlled capacitor based on a reverse biased p-n junction) tuning. As the voltage applied to the varactor is varied, the oscillator frequency changes. The varactor typically enables frequency changes of up to 100 ppm.
Although the varactor ideally allows for continuously variable capacitance, practical applications use a digital-to-analog converter (DAC) to provide the varactor voltage in response to a digital input code. The DAC output and thus the voltage across the varactor is quantized in discrete steps. The number and size of the steps are determined by the total dynamic range of the DAC and the resolution required.
One disadvantage of this architecture is that the varactor size required for sufficient tuning range effectively ensures that the varactor must be an off-chip component. The required use of off-chip controllable variable components is undesirable for cost or space concerns.
SUMMARY OF THE INVENTION
In view of limitations of known systems and methods, methods and apparatus for tuning a digitally controlled crystal oscillator to a desired frequency are provided.
One method includes the step of providing a DCXO having a coarse tuning array and a fine tuning array of capacitors fabricated on a same integrated circuit die. The coarse array is adjusted until the difference between the desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the coarse array is varied until the required change in capacitance is less than the capacitance associated with the least significant bit of the coarse tuning array. The fine tuning array is adjusted until the output frequency substantially matches the desired frequency. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array.
A DCXO apparatus includes a coarse tuning array of capacitors providing a first range of tuning capacitance and a fine tuning array of capacitors providing a second range of tuning capacitance. The coarse and fine tuning arrays are coupled in parallel to form a first segmented capacitor network. The coarse and fine tuning arrays are formed on a same integrated circuit die. In one embodiment, the coarse tuning array is a binary weighted switched capacitor network and the fine tuning array is a thermometer coded switched capacitor network.
A DCXO apparatus includes at least one segmented switched capacitor network providing a capacitance that is a nonmonotonic function Z of a composite input code. A processor is coupled to provide the composite input code. The DCXO output frequency varies in response to the composite input code. In one embodiment, the segmented switched capacitor network includes an n-bit binary weighted coarse tuning array of capacitors and an m-bit thermometer coded fine tuning array of capacitors. In one embodiment, the thermometer coded array comprises unit capacitances C
T
of substantially the same value. The least significant bit of the binary weighted array has an associated capacitance C
B
. In one embodiment 2
m
C
T
<C
B
. In an alternative embodiment, 2
m
C
T
≧C
B
.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
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Takahiro Miki; et al., “An 80 MHz 8b CMOS D/A Converter”, 1986 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp 132-133 (Feb. 1986).
C-H Lin, et al.; “A 10b 250MSample/s CMOS DAC in 1 mm2”, 1998 IEEE International Solid-State Circuits Conference, pp. 14.1-1 -14.1-11 (Feb. 1998).
Georgantas, et al., “Low Power RF to Baseband Interface for Multi-Mode Portable Phones”, European Low Power Initiative for Electronic System Design, EP 25702 I-MODE (Intracom, Institute for Communication and Computer Systems-National Technical University of Athens, 1999).
Frey Douglas R.
Pietruszynski David M.
Davis William D.
Davis & Associates
Nguyen Minh
Silicon Laboratories Inc.
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