Digitally controlled crystal-based jitter attenuator

Details Digitally controlled crystal-based jitter attenuator Digitally controlled crystal-based jitter attenuator

1990-08-07

1992-11-10

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328133, 307262, 307271, 331158, 331179, 375118, 375119, 375120, H03L 700, H03D 1300

Patent

active

051627469

ABSTRACT:
A circuit for attenuating phase jitter on an incoming clock signal includes a digitally controlled oscillator, a phase lock loop including a phase detector, and a dithering circuit. The oscillator is capable of generating N discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase lock loop provides a total of C.times.N.times.NB frequencies. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit. The dithering circuit modulates the oscillator signal to reduce inadequate rejection behavior when the incoming clock frequency is substantially the same as one of the N selectable frequencies of the oscillator divided down to match the frequency of the incoming clock.

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IEEE Standard Dictionary of Electrical and Eletronic Terms; Jul. 20, 1984; p. 149.

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