Digitally controlled analog delay locked loop (DLL)

Details Digitally controlled analog delay locked loop (DLL) Digitally controlled analog delay locked loop (DLL)

2001-07-31

2003-09-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S277000

Reexamination Certificate

active

06628154

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for Delay Locked Loops (DLLs) generally and, more particularly, to a method and/or architecture for a digitally controlled analog Delay Locked Loop (DLL).
BACKGROUND OF THE INVENTION
Some applications can require that data be valid less than 0.35 ns (250 MHz) from a rising clock edge. The clock to data valid (tco) time and the data output hold time (tdoh) dictate the data valid window. Also, the duty cycle of the data can be required to follow the duty cycle of the clock so that the data valid window is not reduced. A zero delay buffer that tracks the clock jitter and duty cycle can be used to meet the requirements.
A conventional zero delay buffer that tracks the clock jitter and duty cycle can include a Delay Locked Loop (DLL). The DLL can generate a phase-adjusted version of an input clock such that a desired edge (e.g., rising or falling) of the DLL clock occurs a time tco before a corresponding edge of the input clock. The phase-adjusted clock can be used to clock data out of a chip so that the data to input clock time is ideally zero.
The DLL is a closed loop system that adjusts the propagation through a delay line such that the delay is equal to the clock period minus the clock to output delay. A phase detector and filter adjust the delay line until a feedback clock is delayed 360 degrees (i.e., phase aligned) with respect to the input clock. Since the compensation delay can be set equal to the time tco, the delay line can have a delay equal to the clock period minus the time tco.
Every cycle the DLL makes an adjustment with the phase detector and filter that corresponds to a phase adjustment in the delay line. The adjustment determines the resolution of the DLL. A fine adjustment corresponds to a small phase adjustment (high resolution) and a coarse adjustment corresponds to a large phase adjustment (low resolution). The DLL needs to have a fast lock time and a fine resolution for low jitter. A fast lock time requires a coarse adjustment in the delay line and a fine resolution requires a fine adjustment in the delay line.
Conventional DLLs either use a digital delay line or an analog delay line. A digital delay line can provide fast lock time at the cost of resolution. An analog delay line can provide good resolution but can require lock acquisition aids such as changing charge pump currents that can cause problems.
Referring to
FIG. 1
, a block diagram of a circuit
10
is shown illustrating an analog DLL. The circuit
10
includes a phase detector
12
, an analog delay line
14
, a compensation delay circuit
16
, a charge pump
18
and an analog loop filter
20
. The phase detector
12
is implemented without a dead zone. The analog delay line
14
can provide minimal jitter. The circuit
10
integrates phase error onto a capacitor in the filter
20
. Since the phase error is integrated onto a capacitor and the phase detector does not have a dead zone, the circuit
10
can provide low clock jitter or fine resolution.
To reduce jitter of the signal DLL_CLOCK, the bandwidth of the DLL
10
can be reduced. The bandwidth is reduced when the capacitance of the loop filter
20
is made large and/or the current from the charge pump
18
is made small. With reduced bandwidth, every up/down cycle of the phase detector only adjusts the phase of the signal DLL_CLOCK by a small amount or not at all when the reference clock REF_CLOCK and the feedback signal FBK have zero degrees of phase error. For coarse adjustment, the bandwidth of the DLL can be made wider by decreasing the capacitor size and/or increasing the charge pump current. For large bandwidths, every up/down cycle of the phase detector adjusts the phase of the signal DLL_CLOCK by a greater amount than for the fine adjustment (small bandwidths).
The analog DLL
10
can provide good resolution. However, using lock acquisition aids that change the charge pump currents or the loop filter can make designing for stability complicated. Also, the analog DLL
10
is limited as to how fast lock can be obtained. In addition, different locking methods can be difficult to implement; such as a binary search.
Referring to
FIG. 2
, a block diagram of a circuit
30
is shown illustrating a digital DLL. The circuit
30
includes a phase detector
32
, a coarse digital delay line
34
, a fine digital delay line
36
, a compensation delay
28
and a digital loop filter
40
. The digital DLL
30
can yield a smaller (size), faster locking, and easier migrating DLL. The digital DLL
30
uses the coarse delay line
34
to get close to lock and the fine delay line
36
to obtain and maintain lock. The charge pump and filter (i.e., elements
18
and
20
of
FIG. 1
) are replaced by the digital loop filter
40
. The digital loop filter
40
includes an up/down counter that only increments/decrements every M up/down cycles, where M is determined by the filter size.
The digital DLL
30
can be less complicated and has a faster lock time than the analog DLL
10
. The digital DLL
30
can be easier to migrate to other technologies. The digital DLL
30
can be smaller than the analog DLL
10
because there is no large loop filter. However, since the fine delay line is a digital element, the resolution is limited to some amount. Also, since the phase error is not integrated, the output can have a dead zone where the digital DLL
30
does not respond until a phase error reaches a particular magnitude. When the particular magnitude of phase error occurs, the DLL
30
is adjusted by the fine adjust.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising an analog delay line and a control circuit. The analog delay line may be configured to generate an output signal in response to an input signal, a first control signal, and a second control signal. A phase of the output signal may be (i) coarsely adjustable with respect to the input signal in response to the first control signal and (ii) finely and continuously adjustable in response to the second control signal. The control circuit may be configured to generate the first and the second control signals in response to the input signal and the output signal.
The objects, features and advantages of the present invention include providing a digitally controlled analog delay locked loop that may (i) provide fine resolution, (ii) have fast lock acquisition, (iii) provide a wide locking range, (iv) eliminate need for fuses or metal optioning for different speed sorts, (v) provide lower speed sorts that have the same resolution as higher speed sorts, and/or (vi) be used in applications that need a zero delay buffer including memory chips that need a small clock to output delay.


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