Digitally calibrated delta-sigma analog-to-digital converter

Details Digitally calibrated delta-sigma analog-to-digital converter Digitally calibrated delta-sigma analog-to-digital converter

1988-04-13

1990-07-24

Shoop, Jr., William M.

Coded data generation or conversion

Converter calibration or testing

341143, H03M 110

Patent

active

049438077

ABSTRACT:
A self-calibrated analog-to-digital converter with a corrected output includes an analog modulator (18) for receiving an analog input voltage and outputting a pulse train having a value proportional to the analog input voltage. The pulse train is filtered by a digital filter (20) which has the output thereof input to a calibration module (24). The calibration module (24) is controlled by a calibration control circuit (28) and is operable to correct the output to account for offset and gain errors. Prestored calibration parameters in a register (30) are utilized for this compensation. In a self-calibration mode, the control circuit (28) is operable to control a calibration multiplexer (12) to select a zero-scale input voltage on a terminal (16) and a full-scale reference voltage on a terminal (14) for input to the modulator (18). The multiplexer (12) is controlled to selcet the zero-scale reference to calculate an offset value for storage in the register (30) and then subsequently select the full-scale reference to calculate a scale factor for storage in the register (30 ). The self-calibration mode utilizes a settling counter (36) to insure that the output of the filter (20) has settled prior to making any calculations.

REFERENCES:
patent: 3725903 (1973-03-01), Kosakowski
patent: 4186384 (1980-01-01), Acker
patent: 4338589 (1982-07-01), Engel et al.
patent: 4364027 (1982-12-01), Murooka
patent: 4509037 (1985-04-01), Harris
patent: 4588979 (1986-05-01), Adams
patent: 4674062 (1987-06-01), Premerlani
patent: 4796004 (1989-01-01), Rich et al.

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