Digitally adjusted high speed analog equalizer

Details Digitally adjusted high speed analog equalizer Digitally adjusted high speed analog equalizer

2007-08-07

2007-08-07

Ha, Dac V. (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

C375S350000, C708S323000

Reexamination Certificate

active

10394844

ABSTRACT:
A high speed CMOS-implemented equalizer architecture as described herein utilizes a digitally controlled analog equalization scheme to equalize intersymbol interference present in an input signal. The equalizer structure includes an inductor high frequency gain boosting stage and a feed forward high frequency equalizer stage connected in series. The equalization performed by each of these gain boosting stages is controlled by one or more digital control signals. The combination of these stages results in the equalization of both amplitude and phase distortion. The equalizer architecture is suitable for use with communication systems that operate at 11.2 Gbps speeds.

REFERENCES:
patent: 6795494 (2004-09-01), Phanse et al.
patent: 6975678 (2005-12-01), Le et al.
patent: 7003228 (2006-02-01), Wang et al.

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