Digitally adjustable picosecond delay circuit

Details Digitally adjustable picosecond delay circuit Digitally adjustable picosecond delay circuit

1995-05-22

1996-04-09

Wong, Peter S.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327281, 327288, 327394, H03K 513

Patent

active

055065341

ABSTRACT:
A digitally adjustable time delay circuit which is able to precisely and selectively provide fine delay steps increments, which increments can be one nth of the delay time of one CMOS inverter, including means to adjust the total range of the delay and size of each delay step.

REFERENCES:
patent: 3737673 (1973-06-01), Suzuki
patent: 4482826 (1984-11-01), Ems
patent: 4709170 (1987-11-01), Li
patent: 4742254 (1988-05-01), Tomisawa
patent: 4806804 (1989-02-01), O'Leary
patent: 4899071 (1990-02-01), Morales
patent: 5012141 (1991-04-01), Tomisawa
patent: 5012142 (1991-04-01), Sonntag
patent: 5028824 (1991-07-01), Young
patent: 5111085 (1992-05-01), Stewart
patent: 5175452 (1992-12-01), Lupi et al.
patent: 5258659 (1993-11-01), Kannegundla
patent: 5278522 (1994-01-01), Atriss et al.
patent: 5302920 (1994-04-01), Bitting
patent: 5317219 (1994-05-01), Lupi et al.
Patent Abstracts of Japan vol. 10, No. 213 (E-422)(2269) 14 Mar. 1986 & JP-A-61 052 022 (Hitachi).

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