Digitally adjustable amplifier for integrated circuit

Amplifiers – With amplifier condition indicating or testing means

Reexamination Certificate

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C330S009000

Reexamination Certificate

active

07135916

ABSTRACT:
A digitally adjustable amplifier with adjustable input offset voltage and amplification parameters for use in integrated circuits. Such adjustments are carried out by a binary counter which controls a non-binary weighting element which by a non-binary weighting of each stage to the next stage intentionally has a non-linearity of the ideal characteristic curve because of greater negative steps at increasing value count so that the steps remain below one least significant bit. Thus greater errors even can be tolerated, and a desired value can be very closely attained.

REFERENCES:
patent: 6242974 (2001-06-01), Kunst
patent: 6252454 (2001-06-01), Thompson et al.
patent: 6262625 (2001-07-01), Perner et al.
patent: 6642784 (2003-11-01), McMorrow
Massimo Lanzoni et al.: Automatic and Continuous Offset Compensation of MOS Operational Amplifiers Using Floating-Gate Transistors; IEEE Journal of Solid-State Circuit, vol. 33, No. 2, Feb. 1998.
Hendrik van der Ploeg et al.: A 2.5-V 12-b 54 Msample/s 0.25-m CMOS ADC in 1-mm2 With Mixed-Signal Chopping and Calibration; IEEE Journal of Solid-State Circuits, vol. 36, No. 12, Dec. 2001.
R. Razavi: “Precision Techniques” Chapter 8, pp. 198-231 from “Principles of Data Conversion System Design”; IEEE Press, 1995.

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