Dynamic magnetic information storage or retrieval – General processing of a digital signal – Data clocking
Reexamination Certificate
1999-05-06
2001-10-23
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Data clocking
Reexamination Certificate
active
06307696
ABSTRACT:
TECHNICAL FIELD
The present invention is in the field of magnetic recording of digital data and, more specifically, concerns rapid synchronization in the timing loop of a magnetic read channel such as those found in computer disk drives.
BACKGROUND OF THE INVENTION
Hard disk drives have been in use for nearly twenty years and are found in most computers, as well as other types of electronic systems where non-volatile recording of large quantities of digital data is required. Many techniques have been developed over the years to improve the performance of hard disk drives, including magneto-resistive read/write heads, various RLL encoding schemes and the now well-known if not ubiquitous PRML (partial response maximum likelihood) read channel. One of the important improvements adopted early on in disk drive evolution was the “servo wedge”—areas on the magnetic recording surface where timing and control information are stored, generally interspersed between encoded user data storage regions. For example, a typical data track on a hard disk includes a series of spaced-apart data regions, alternating with embedded servo regions. The data regions are typically encoded according to a PRML code specification. There may be on the order of 100 or more servo regions embedded within each concentric data track, as further explained later with reference to the drawings. Each servo region includes information used by the head position servo for precisely positioning and tracking the head over the particular track. Each servo region also includes a “preamble pattern,” typically a repeating pattern of plus and minus magnetic flux transitions that will reproduce as a sine wave analog signal in the read channel for the purpose of synchronizing the servo demodulator phase locked loop (PLL) to the servo position data stored on the recording surface. Interspaced with the servo wedges are data sectors where the digital data is stored on the magnetic media. Each data sector likewise includes a preamble sine wave pattern that is used for synchronizing the read channel PLL to data being read off the magnetic disk. A representative disk drive that employs the technologies summarized above is described in detail in commonly-assigned U.S. Pat. No. 5,345,342 entitled “DISK DRIVE USING PRML SYNCHRONOUS SAMPLING DATA DETECTION AND ASYNCHRONOUS DETECTION OF EMBEDDED SECTOR SERVO.”
At the beginning of a disk read operation or, more precisely, in preparation for each data read operation or servo operation, the read channel timing loop circuitry is re-synchronized to the current preamble pattern. In prior art, this timing acquisition is aided by a combination of either (1) adaptive or two-stage phase-locked loop (PLL) filters; and/or (2) analog Zero-Phase Restart (ZPR) techniques, according to which the voltage-controlled oscillator (VCO) is held for a short time, and then released so as to be aligned with the incoming analog read signals.
Adaptive PLL loop filters improve acquisition performance by increasing the loop bandwidth for a short duration to achieve phase lock; at the cost of increased phase jitter. Then the loop bandwidth is reduced to the steady state value required to meet allowed jitter tolerance. The acquisition improvement is a function of the size of the increase in the loop bandwidth, which in turn is limited by the size of disturbance that the PLL can tolerate without completely losing synchronization.
Analog ZPR circuits function by holding the analog VCO for a short time, and then releasing the oscillator so as to align the VCO phase with the input signal phase. Analog ZPR accuracy is limited by the tolerances of the analog circuitry. The critical tolerances that affect accuracy include that of the sensor that detects the input signal phase; the hold-off circuit that stops the VCO; and the reaction delay time of the controlling circuitry. All of these tolerances conspire to limit the accuracy achievable using the analog hold technique. In view of the foregoing background, the need remains for improvements in rapidly acquiring synchronization to the preamble pattern in a disk drive read channel. Acquisition performance is critically important in a magnetic read channel because the time spent in acquiring or synchronizing to the input signal reduces the time that could otherwise be spent reading user data off the disk. And similarly reducing the size of the preamble pattern translates to better utilization of the recording surface area for user data.
SUMMARY OF THE INVENTION
The present invention seeks to improve timing acquisition performance in a digital PLL by accurately (and quickly) estimating the initial input signal phase, and then initializing the VCO phase to that of the input signal before the PLL commences normal operation. This step function or “jump start” to an accurately estimated phase value enables the PLL to settle and lock very quickly. Simulations and measurements show settling times of about 0.25 microseconds as compared to about 3.5 microseconds with the new ZPR feature turned off.
One aspect of the present invention is an all-digital circuit for improved timing acquisition. Specifically, the invention leverages an interpolating digital timing loop to create an all-digital ZPR circuit that can initialize the correct sampling phase with very high accuracy. The new circuit does not rely on analog circuit tolerances as in the prior art. The improved ZPR function preferably is used in conjunction with a two-stage PLL loop filter to improve timing acquisition performance, although it is useful in a PLL with a first order loop filter as well. The invention takes advantage of a PLL with a digital integrator and phase interpolator in place of the conventional analog VCO.
The new ZPR circuit calculates the initial phase of the input signal, based on an ARCTAN lookup table, although equivalent implementations could be used (RAM, logic, etc.). The arctan lookup is based on a ratio of accumulated sine and cosine components of the input preamble signal. The sampling clock phase is then shifted by the calculated phase error, and then two-stage timing acquisition proceeds. Since the calculation is based on a ratio of accumulated values, gain variations cancel one another out of the calculation, as do analog component variations. The net result of this new ZPR function is an initial phase error that is less than approximately 15% of a symbol interval prior to timing acquisition in the worst case; typically this is nearer to 5%.
Additional objects and advantages of this invention will be apparent from the following detailed description of preferred embodiments thereof which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 5341249 (1994-08-01), Abbott et al.
patent: 5345342 (1994-09-01), Abbott et al.
patent: 5835295 (1998-11-01), Behrens
patent: 5905601 (1999-05-01), Tsunoda
patent: 6067198 (2000-05-01), Zuffada et al.
The Illustrated Dictionary of Electronics, Fifth Edition, p. 453, by Rufus P. Turner et al, published Dec. 1991, by McGraw-Hill, Inc.
Bishop Andrew
Veiga Eduardo G.
Faber Alan T.
Maxtor Corporation
Sigmond David M.
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