Digital voltage level translator circuit

Details Digital voltage level translator circuit Digital voltage level translator circuit

1992-10-02

1994-01-04

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307450, H03K 190175, H03K 1120

Patent

active

052763668

ABSTRACT:
A digital voltage level translator circuit for interfacing circuitry operating at different voltages is described. An inverting digital voltage level translator circuit (11) has an input (12) and an output (13). The input is coupled to a transmission gate (18), an inverter (17), and a gate of a n-channel enhancement MOSFET (22). Transmission gate (18) is enabled by the inverter (17) when the input (12) is at a zero logic level. An output of transmission gate (18) is coupled to a gate of a p-channel enhancement MOSFET (21) and an output of a pull-up circuit (19). A zero logic level at the input (12) enables MOSFET (21) through transmission gate (18) and disables MOSFET (22) generating a one logic level at output (12). A one logic level at the input (12) enables MOSFET (22) transitioning output (13) to a zero logic level. Output (13) to a control input of pull-up circuit (19) and a zero logic level enables pull-up circuit (19) disabling MOSFET (21).

REFERENCES:
patent: 4743782 (1988-05-01), Nelson
patent: 4926070 (1990-05-01), Tanaica
patent: 4958091 (1990-09-01), Roberts
patent: 5144165 (1992-09-01), Dhong

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