Pulse or digital communications – Receivers – Automatic gain control
Reexamination Certificate
2001-09-14
2004-03-16
Vo, Don N. (Department: 2631)
Pulse or digital communications
Receivers
Automatic gain control
Reexamination Certificate
active
06707865
ABSTRACT:
FIELD
The invention relates generally to wireless communication systems and, more particularly, to voltage gain amplifiers within wireless communication systems.
BACKGROUND
One common technique used in wireless communication is code division multiple access (CDMA) signal modulation in which multiple communications are simultaneously conducted over a radio-frequency (RF) spectrum. Some example wireless communication devices that have incorporated CDMA technology include cellular radiotelephones, PCMCIA cards incorporated within computers, personal digital assistants (PDAs) equipped with wireless communication capabilities, and the like.
A conventional architecture for a CDMA receiver includes a radio-frequency (RF) section and an infrared (IF) section. In particular, the received RF signals are typically filtered in the RF section, converted from RF signals to IF signals for further filtering and scaling by a voltage gain amplifier (VGA) in the IF section, and finally converted to baseband signals. The baseband signals are typically passed through an analog-to-digital (A/D) converter to produce digital samples which can be sent to a digital signal processor for tracking and demodulation.
The Zero infrared frequency (Zero IF) architecture is a more recent architecture used in CDMA wireless communication devices. Unlike other conventional architectures, the Zero IF architecture converts incoming RF signals directly into baseband signals without first converting the RF signals to IF signals. In particular, the Zero IF architecture makes use of a digital VGA that scales the digital samples produced by the A/D converter. In this manner, the Zero IF architecture eliminates the need for various IF components, including an IF mixer, an IF VGA and IF filters.
In the heterodyne architecture with an IF section, the IF-VGA controlled by an automatic gain control unit (AGC) is responsible for either expanding or compressing the signal such that it fits in the relatively narrow dynamic range of the A/D converter. The A/D converter can then produce small bit-width (typically 4 bits) numbers so that rest of the hardware that performs signal processing can be simplified. In the Zero-IF architecture however, due to the absence of the IF VGA, the A/D converter is typically designed to have much larger dynamic range resulting in large bit-width numbers at the output.
Although the Zero IF architecture eliminates the need for IF components, the architecture may require more complicated baseband components, primarily due to the relatively large digital signals (typically 18 bits) generated by the A/D converter. Consequently, a digital VGA is implemented at baseband to scale the large bit-width signals from the A/D converter. The Zero IF architecture may implement a relatively wide multiplier (typically an 18-bit by 18-bit multiplier) to scale the large digital signals. In addition, the digital VGA typically includes a relatively large lookup table (LUT) (often exceeding a kilobyte or more) to convert values received from the AGC unit from logarithmic units in decibels (dB) to linear values for controlling the gain of the digital VGA. In operation, for example, the digital VGA multiplies the linear digital signals received from the A/D converter by a linear gain value obtained from the LUT. For these reasons, wireless communication devices incorporating the Zero IF architecture may have significant cost even though the IF components have been eliminated.
SUMMARY
In general, the invention is directed toward a digital voltage gain amplifier (digital VGA) that operates within the logarithmic domain. In particular, the digital VGA scales digital input values in accordance with logarithmic gain values. Among other advantages, properties of the logarithmic domain are exploited to replace the complex multiplier of a conventional VGA with a simple and relatively inexpensive adder. Additional techniques are described to significantly reduce the size of one or more LLTTs implemented within the digital VGA. In this manner, the invention can realize a much more simple, lower cost design of a digital VGA.
Although not so limited, the digital VGA is particularly useful within CDMA wireless communication devices that incorporate the Zero IF architecture. The invention greatly simplifies the manner in which relative large digital signals can be processed, reducing the complexity, memory space and cost of the wireless communication device. Other non-CDMA Zero-IF architectures can also benefit from the invention.
In one embodiment, the invention comprises a digital voltage gain amplifier. The amplifier may include a logarithmic conversion unit that converts a baseband signal from a linear domain to a logarithmic domain and an adder that sums the converted baseband signal with a gain signal to produce a scaled baseband signal. In addition, the amplifier may include an exponential conversion unit that converts the scaled baseband signal from the logarithmic domain to the linear domain.
In another embodiment, the invention comprises a wireless communication device. For example, the wireless communication device may include an antenna that receives an RF signal and an RF mixer that generates a baseband signal from the RF signal. In addition, the wireless communication device may include the voltage gain amplifier described above to scale the baseband signal. The wireless communication device may also include digital signal processor that processes at least part of the scaled baseband signal in the linear domain.
In still other embodiments, the invention may comprise one or more methods. For example, a method may include converting a baseband signal from a linear domain to a logarithmic domain, and adding the converted baseband signal to a gain to generate a scaled baseband signal. The method may also include converting the scaled baseband signal from the logarithmic domain to the linear domain. The conversions may utilize lookup tables. Additional techniques can be used to reduce the size of the lookup tables and thus reduce memory requirements.
In yet another embodiment, the invention can avoid the use of a multiplier in a digital VGA. For example, a multiplication function followed by optional truncation can be performed by first converting the two inputs to be multiplied into the logarithmic domain. The input signals can then be added or subtracted in the logarithmic domain before being converted back to a linear domain with just enough bits to mimic the original truncation operation.
The invention can provide a number of advantages. For example, the invention can provide a more simple, lower cost design of a digital VGA for use in Zero IF architecture. In particular, the invention may eliminate the need for a complex and relatively expensive multiplier, which can be replaced with a much more simple and inexpensive adder. In addition, because the inventive amplifier operates in the logarithmic domain, the need to convert the gain values to a linear domain can be simplified, or avoided altogether. In one embodiment, for example, a digital VGA scales digital input values within the logarithmic domain using logarithmic gain values in units of decibels. In that case, the gain values can be provided to the adder without any conditioning or conversion.
The invention may also significantly reduce memory requirements in a digital VGA by using techniques to reduce the size of one or more LUTs implemented in the digital VGA. In particular, an exponential conversion unit may saturate a baseband signal in the logarithmic domain prior to converting the baseband signal back into a linear domain. The saturation prior to lookup can reduce the size (i.e., width) of the individual entries in the LUT, thus reducing the amount of memory required for the LUT. In addition, a logarithmic conversion unit may utilize different LUTs for the exponent and the mantissa of a floating point number, as described in detail below, which can drastically reduce memory requirements. In particular, only a portion of the mantissa values may be stored in the
Brown Charles D.
Kordich Donald
Qualcomm Incorporated
Vo Don N.
Wadsworth Philip
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