Digital video signal encoding arrangement, and corresponding dec

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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368135, 368 12, 382 56, 375 25, H04N 712, H04N 1106

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active

049204149

ABSTRACT:
A digital video signal encoding arrangement comprising a correlation reducing circuit receiving said digital signals which are representative of the luminance or the chrominance of a certain number of elements of a picture which has been divided into blocks, a scanning conversion circuit (30), a normalization circuit (50), a quantizing circuit (60), a circuit (70) for encoding said quantized values and a rate controlling circuit (80). This arrangement is characterized in that its normalization circuit itself comprises: (a) a weighting coefficient storage memory (51) which is addressed on the one hand by an index i indicating the position in the current block, and on the other hand by a value representative of the activity of this block; (b) a standard calculating circuit (52) on the basis of a mean standard value produced by the rate controlling circuit and also on the weighting coefficient supplied; (c) a circuit (59) for dividing by the coefficient K.sub.i the output of said standard calculating circuit.

REFERENCES:
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patent: 4541012 (1985-09-01), Tescher
patent: 4707738 (1987-11-01), Ferre et al.
patent: 4774587 (1988-09-01), Schmitt
patent: 4780761 (1988-10-01), Daly et al.
patent: 4797742 (1989-01-01), Sujiyama et al.

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