Digital VFO phase control device

Details Digital VFO phase control device Digital VFO phase control device

2001-04-18

2004-08-10

Hudspeth, David (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

C360S046000, C360S055000, C360S048000, C360S031000, C360S039000, C360S040000

Reexamination Certificate

active

06775082

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase control device of a digital VFO and particularly relates to a digital VFO phase control device capable of detecting the phase shift of input data and generating an optimum phase relationship between input data and output WINDOW pulse with a simple circuit arrangement in the phase correction in a digital VFO during serial data reproduction.
2. Description of Related Art
A VFO (Variable Frequency Oscillator) is employed particularly when the data of a magnetic recording disk is reproduced.
The VFO is normally realized by an analog circuit. The analog circuit is required to adjust a resistance value and a capacitive value, so that it is difficult to design the analog circuit and it is difficult to reduce a chip area.
Recently, demand for digitizing a VFO rises. To meet this demand, there is proposed digitizing a VFO using a counter as disclosed by, for example, Unexamined Japanese Patent Publication (KOKAI) No. 3-227123.
The circuit disclosed by the above Unexamined Japanese Patent Publication is shown in FIG.
7
.
In
FIG. 7
, reproduced data (
31
) is a signal outputted from a floppy disk drive. A scaling circuit (
32
) generates reference data (
32
a
) having a width of one clock relative to a reference clock from the reproduced data (
31
) using the reference clock. A counter circuit (
33
) is a binary counter having a reset function for incrementing a counter value by the reference clock. A symbol MSB indicates the most significant bit. A D-type flip-flop (
34
) serves as a divider and generates an output clock. The output clock in
FIG. 7
corresponds to a WINDOW pulse (
110
) shown in FIG.
1
.
Description will now be given while taking a case where a data transfer rate is 500 Kbps and the reference clock shown in
FIG. 7
(corresponding to a system clock (
20
) shown in
FIG. 2
) has a frequency of 12 MHz as an example.
In this case, if the cycle of the counter (
33
) generating output clocks is set at 12 in decimal system, the cycle of input data accords with that of an output clock.
In a circuit shown in
FIG. 7
, a counter value is set at 6 so that reproduced data is at the center of either the High width or Low width of the output clock per reproduced data to promptly make a phase correction. Due to this, if a peak shift which is the feature of data recorded magnetically is included in the reproduced data, an erroneous correction is made, thereby make it disadvantageously impossible to accurately reproduce data.
An example of an erroneous correction to the peak shift pair in the constitution of
FIG. 7
is shown in FIG.
8
. An output clock indicated by a solid line in
FIG. 8
shows a waveform when the peak shift is erroneously corrected and an output clock indicated by a dotted line shows a waveform when the peak shift is not corrected. It is assumed that the data to be reproduced is “11” and that a peak shift in which these both bits shift in the opposite direction from the center occurs.
Originally, if reproduced data occurs, the output clock should be outputted at High timing. In the example of the constitution shown in
FIG. 7
, if a peak shift occurs, the reproduced data at a time t
10
is deviated from the High timing of the output clock.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new digital VFO phase control device characterized in that the disadvantages of the conventional technique stated above can be overcome, and the phase shift of input data can be detected and an optimum phase relationship between input data and output WINDOW pulse can be generated with a simple circuit constitution in the correction of the phase of the digital VFO during serial data reproduction, and particularly an optimum phase relationship between input data and an output WINDOW pulse can be maintained without being influenced by a peak shift and a sudden phase shift.
To obtain the above object, the present invention basically adopts the following technique constitution.
The first aspect of the present invention is a digital VFO phase control device comprising: an output signal generation means for generating an output signal having the predetermined phase relationship with an input signal of the digital VFO phase control device, a phase difference detection means for detecting a phase difference between the input signal and the output signal, a first correction value output means for outputting a correction value for correcting a phase of the output signal based on a phase difference detected by the phase difference detection means, a second correction value output means for outputting a preset correction value for correcting a phase of the output signal based on a phase difference detected by the phase difference detection means, a comparison means for detecting whether or not the phase difference detected by the phase difference detection means being within a predetermined range, and a correct value selection means for selecting either one of a correction value outputted by the first correction value output means and a correction value outputted by the second correction value output means based on a comparison result of the comparison means, and controlling a phase of the output signal utilizing said selected correction value.
In the second aspect of the present invention, the output signal generation means comprises a counter.
In the third aspect of the present invention, the first correction value output means comprises a phase difference averaging means for averaging phase differences detected by the phase difference detection means and a correction value calculation means for obtaining the correction value based on an average value calculated by the phase difference averaging means, and the correction value calculation means includes an arithmetic operation means for preventing excessive correction.
In the fourth aspect of the present invention, the first correction value output means obtains the correction value from an expression of {n+(C−A)/M+1}, where n is a counter value of the counter when the phase difference detection means receiving the input signal, C is a pre-established value, A is an average value calculated by the phase difference averaging means, and M is a coefficient for preventing excessive correction.
In the fifth aspect of the present invention, the pre-established value C is equal to MAX/2, where MAX is maximum value of the counter.


REFERENCES:
patent: 63-237201 (1988-10-01), None
patent: 64-47127 (1989-02-01), None
patent: 01272324 (1989-10-01), None
patent: 3-227123 (1991-10-01), None
patent: 4-310675 (1992-11-01), None
patent: 5-242610 (1993-09-01), None
patent: 5-303706 (1993-11-01), None
patent: 7-56717 (1995-06-01), None
patent: 2560406 (1996-09-01), None
patent: 10-283737 (1998-10-01), None
Guonai et al, “Novel Phase Locked Loop with Digital Control Techniques”, May 8-11, 1989, IEEE International Symposium Circuits and Sytems, vol. 2, pp. 1411-1414.*
Fuminori et al, “Efficient Digital Techniques for Implementing a Class of Fast Phase-Locked Loops (PLL's)”, Dec. 1996, IEEE Transactions on Industrial Electronics, vol. 43, No. 6, pp. 616-620.

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