Digital-type delay locked loop with expanded input locking range

Details Digital-type delay locked loop with expanded input locking range Digital-type delay locked loop with expanded input locking range

1998-05-06

1999-12-21

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327155, 327161, H03L 706

Patent

active

060054263

ABSTRACT:
A low-jitter delay locked loop having an expanded phase locking range without the necessity of setting the initial delay is provided. The loop is to be supplied by a system clock and includes a pulse generator receiving the system clock for generating a first pulse signal and a second pulse signal in response to a triggering signal, a delay device receiving the system clock for providing a delayed clock in response to a control signal, a frequency-reducing device for frequency-reducing the system clock into a first clock in response to the first pulse signal and frequency-reducing the delayed clock into a second clock in response to the second pulse signal, and a comparator for comparing the first and second clocks to generate the control signal.

REFERENCES:
patent: 4817199 (1989-03-01), Wallraff
patent: 5479458 (1995-12-01), Tanaka
patent: 5572557 (1996-11-01), Aoki

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