Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1988-07-27
1991-03-26
Safourek, Benedict V.
Pulse or digital communications
Spread spectrum
Direct sequence
375118, 360 32, H04L 702
Patent
active
050035592
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a digital transmission system for transmitting data by a digital audio interface (hereinafter abbreviated as "DAI"), and more particularly to a digital transmission system which is provided in its receiver side with an oscillator for generating a master clock which is supplied directly to a D/A converter as well as to its transmitter side through the DAI for synchronization with digital reading, wherein reproduced data is transmitted through the DAI to the receiver side to thereby reduce the occurrence of jitter in a timing for D/A conversion.
BACKGROUND OF THE INVENTION
A digital audio interface (DAI) transmission system as shown in FIG. 1 is known as one of digital transmission systems. Since the DAI transmits L-channel and R-channel data through a single digital cable, it employs a time-division-multiplexing transmission system which permits the L-channel and R-channel data to be alternately transmitted and received, as shown in FIG. 6A. If the sampling frequency is chosen to be, for example, 44.1 kHz as in the case of the compact disc, 44100 samples of the respective R-channel and L-channel data, that is, totally 88200 samples of data of both the channels are transmitted per second. One channel data period (word) is 11.34 sec. One word is formed of 32 bits which are divided, for example, as shown in FIG. 6B. Specifically, in the same figure, the first four bits are assigned to be a SYNC portion for synchronization in which a preamble, later referred to, is inserted. The subsequent portion, for storing audio data, has a capacity of 24 bits. However, in many cases audio data is formed of 16 bits as the compact disc, so that only 16 bits from the end are presently used. The last four bits are assigned to be a control portion for storing information added to the data such as ON/OFF of emphasis, sub-code and so on.
The data thus arranged is subjected to a so-called biphase mark modulation in which data "0" corresponds to one transition and data "1" corresponds to two transitions as shown in FIG. 6C. However, the SYNC portion is an exception and written with a particular pattern called "preamble". In the preamble, the correspondent relationship between the transition and the data values is ignored so that this portion has a high-level period longer than any other portion.
In FIG. 1, reference numeral 1 designates a transmitter such as a compact disc player, and 2 a receiver such as a D/A converter system. The transmitter 1 comprises an oscillator 3 for generating a master clock of a predetermined frequency, a data read-out circuit 4 for reading out data from a recording medium (not shown), for example a compact disc or the like, on the basis of the master clock, and an encoder 5 for encoding the data read out on the basis of the master clock in accordance with a DAI format signal.
The receiver 2 comprises a detecting circuit 6 for detecting a synchronizing signal having a frequency, for example, double the frequency of the audio data sampling frequency fs from the above-mentioned DAI format signal, a PLL circuit 7 for generating a clock signal having a frequency, for example, 256 times the sampling frequency fs and phase-locked with the detected synchronizing signal, a decoder 8 for decoding the input signal on the basis of the clock signal, and a D/A converter 9 for converting the digital decoded signal to an analog signal.
The encoder 5 of the transmitter 1 supplies the receiver 2 with a DAI format signal Rx as shown in FIG. 5A. The upper portion of FIG. 5A shows in detail the waveform of the DAI format signal Rx, and the lower portion of FIG. 5A typically shows the same DAI format signal Rx. Such the DAI format signal Rx is supplied to the detecting circuit 6. In the detecting circuit 6, a synchronizing signal 2FSR having one edge (a rising edge) per one SYNC as shown in FIG. 5B is detected. The synchronizing signal 2FSR has the frequency double the sampling frequency fs, as described above.
The synchronizing signal 2FSR from the detecting circuit 2 is
REFERENCES:
patent: 4381525 (1983-04-01), Senoo et al.
patent: 4617599 (1986-10-01), Noguchi et al.
patent: 4644546 (1987-02-01), Doi et al.
Inayama Minoru
Kanai Takashi
Bocure Tesfaldet
Safourek Benedict V.
Sony Corporation
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