Pulse or digital communications – Equalizers – Automatic
Reexamination Certificate
2000-03-09
2004-08-17
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Equalizers
Automatic
C375S219000, C370S286000, C379S406010
Reexamination Certificate
active
06778599
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data communication devices, and specifically to adaptive digital data transceivers.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram that schematically illustrates a generalized multi-rate filter
10
, having an output sample rate that is an arbitrary rational fraction, L/M, of the input sample rate. This scheme is described by Vaidyanathan in
Multirate Systems and Filter Banks
(Prentice Hall, 1993), which is incorporated herein by reference, pages 100-133. An input signal x(n) is first upsampled by an integer factor L, typically using an interpolator
12
. The upsampled signal is filtered by a digital filter block
14
with response H(z). A decimator
16
downsamples the filtered signal by another integer factor M. L may be either greater than or less than M. The output signal y(n) from filter
10
has a sample rate L/M times the sample rate of the input signal x(n).
The use of fractionally-spaced digital equalizers and echo cancellers is also known in the art. Such devices, which process signals at a rate that is higher than the symbol rate, have been found to give improved performance over synchronous devices. The taps of a fractionally-spaced time-domain equalizer, for example, are separated in time by less than the interval between the symbols. Typically, the tap interval is an integer dividend of the symbol interval, so that the equalizer operates at a rate that is an integer multiple of the symbol rate. A comprehensive discussion of such devices is presented, for example, by Gitlin et al., in
Data Communications Principles
(Plenum Press, 1992), which is incorporated herein by reference. (See particularly pages 488-499 and 528-535 regarding equalizers, and pages 607-661 regarding echo cancellation.)
SUMMARY OF THE INVENTION
It is an object of some aspects of the present invention to provide improved devices and methods for multi-rate signal processing.
In preferred embodiments of the present invention, a digital data transceiver comprises a transmitter and a receiver, which respectively transmit an output signal and receive an input signal, representing sequences of data symbols with a predetermined symbol rate. The input signal is sampled by an analog front end of the receiver at a processing rate that is a non-integer rational multiple of the predetermined symbol rate, preferably a non-integer multiple less than two. An echo canceller generates, responsive to symbols transmitted by the transmitter, an echo estimation signal at the processing rate, for subtraction from the sampled input signal. Following echo cancellation, a feed-forward equalizer receives the signal at the processing rate and generates a forward-equalized signal, while at the same time downsampling the signal back to the original symbol rate. The forward-equalized symbols are processed by decision circuitry, preferably including a slicer and decision feedback equalizer, as is known in the art, to output a stream of estimated data symbols.
By comparison with multi-rate transceivers known in the art, the architecture of the present transceiver is unique in that both the echo canceller and the feed-forward equalizer operate at the same, non-integer multiple rate. The transceiver thus achieves the performance benefit of fractionally-spaced processing, with a reduced number of computations per symbol interval relative to that required for implementation of double-rate processing, as is commonly used in transceivers known in the art.
In some preferred embodiments of the present invention, the echo canceller and equalizer comprise multi-phase (or multi-section) filters, with a plurality of taps. For each of the taps, the filter stores a number of groups of filter coefficients, such that each group contains one filter coefficient for each of the plurality of taps. The samples in the taps are multiplied by the filter coefficients in each of the groups in turn so as to generate tap outputs, which are summed to give a partial sum for that group. The filter coefficients in each group are computed so as to combine the desired filtering effect (such as echo cancellation or equalization) with interpolation between the samples. Therefore, multiplying the samples by the coefficients in the different groups with the appropriate timing effectively upsamples the filter input by a factor equal to the number of groups.
A switch selects among the partial sums for the different groups at a downsampling rate that is an integer dividend of the product of the input sample rate times the number of groups. In other words, the multiple groups of filter coefficients effectively upsample the input by a first integer factor equal to the number of groups, and the switch then decimates the partial sums by a second integer factor. The output sample rate of the filter is thus a rational, non-integer multiple of the input sample rate given by the quotient of the first and second integer factors. Substantially any choice of integer factors may be used, although practically 3:2 has been found to give advantageous results with minimal hardware complication. Those skilled in the art will appreciate that multi-rate filters of this type are useful not only in the context of the transceiver described hereinabove, but also in other digital filtering applications.
Preferably, the echo canceller and equalizer comprise adaptive filters, which receive respective error signals responsive to the filter outputs. The multiple groups of coefficients are automatically adjusted responsive to the respective error signals. Preferably, a least-mean-square (LMS) algorithm is used to determine optimal coefficients in all of the groups and then to adjust the coefficients as necessary during operation of the transceiver. Most preferably, in an initial phase of operation of the filter, different starting conditions are applied to the different groups in order to ensure that the coefficients in the different groups have different values, reflecting their role in interpolating between the samples, and thus preventing their erroneously converging to the same values. In a preferred embodiment, the starting conditions are imposed on the equalizer by transmitting a known training sequence of symbols to the receiver.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a digital data receiver, including:
a front end, coupled to receive an input signal transmitted over a communication channel, the signal representing a stream of transmitted symbols with a given input symbol rate, and to generate, responsive to the input signal, a stream of received samples at a processing rate that is a non-integer rational multiple of the input symbol rate;
a feed-forward equalizer, coupled to receive input samples at the processing rate, responsive to the received samples, and to generate forward-equalized samples at the input symbol rate, the feed-forward equalizer including:
a first plurality of taps, arranged in series to receive a succession of the input samples at the processing rate;
a second plurality of registers operative to store filter coefficients in a number of groups, such that each group contains one filter coefficient for each of the first plurality of taps;
a third plurality of multipliers, coupled to multiply the samples in the taps by the corresponding filter coefficients so as to generate respective tap outputs for each one of the groups;
one or more summers, coupled to sum the tap outputs for each one of the groups, thus generating respective group equalized partial sums; and
at least one switch, operative to select among the groups at the input symbol rate, so that the equalized partial sums are output in alternation as the forward-equalized samples; and
decision circuitry, coupled to process the forward-equalized samples so as to generate a stream of estimated symbols at the input symbol rate.
In a preferred embodiment, the input signal includes a Digital Subscriber Line (DSL) signal, and the processing rate is substantially equal to 1.5 times the
Darby & Darby
Ghebretinsae Temesghen
Tioga Technologies
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