Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2003-05-28
2004-11-23
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S144000
Reexamination Certificate
active
06822593
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital to digital Sigma-Delta modulators (&Sgr;-&Dgr; modulator). In particular, it is applicable to digital frequency synthesizers or DMS (Digitally Modulated Synthesizer) circuits. Such circuits are especially used in the radio frequency transmitters of mobile terminals or of stationary stations of a radio communications system.
A digital to digital &Sgr;-&Dgr; modulator is a device for encoding a digital signal using a small number of steps, and a sampling frequency which is high compared to the passband of the signal to be encoded. This device shapes the spectrum of the quantization noise by pushing its power back into a frequency band not occupied by the spectrum of the useful signal. This spectral separation makes it possible, by filtering the encoded signal, to retain a signal-to-noise ratio complying with given specifications.
2. Related Art
A known digital to digital Sigma-Delta modulator comprises:
an input in order to receive a digital input value encoded over a given number N of bits, where N is a specified integer;
an output in order to deliver a digital output value encoded over a given number n of bits, where n is a specified integer less than N; and
one or more Sigma-Delta cells placed between the input and the output of the modulator.
Each cell may be of the first order or of a higher order. When the modulator comprises several cells, the latter may be arranged according to a structure known to the one skilled in the art by the name of “MASH structure”. In this case, the cells are often identical to each other, but this is not mandatory. In particular, some may be of the first order, and others of a higher order.
In all cases, each Sigma-Delta cell comprises, at a minimum, the following elements:
a subtractor comprising a first input, a second input, and an output, the first input being coupled to the input of the modulator in order to receive the digital input value or a value derived therefrom;
an integrator comprising an input coupled to the output of the subtractor, and an output; and
a quantizer having an input coupled to the output of the integrator and an output coupled to the second input of the subtractor. Furthermore, the output of the quantizer is coupled to the output of the modulator in order to deliver the digital output value or a contribution thereto. The quantizer has a specified quantization interval.
In practice, the input of the modulator receives successive values of a digital input signal, occupying a passband much lower than the sampling frequency. The corresponding output values form an output signal, which is a digital signal.
A particularly awkward problem for implementing such a modulator resides in the unpredictable (except for exhaustive simulations which in practice are sometimes unachievable) appearance of limit cycles. These limit cycles depend on the value of the input signal, on the architecture of the &Sgr;-&Dgr; modulator and on the initial conditions. They are apparent from the concentration of a considerable part of the output signal power in a small number of lines (lines with a power value which is higher than the local mean value). These situations impair the desired encoding performance by increasing the power of the encoding noise in the passband of the useful signal.
Analysis of the behaviour of a digital to digital &Sgr;-&Dgr; modulator comes within the study of systems called “sequential Mealy machines” and of non-linear servo-control systems. The “harmonic” analysis of a digital to digital &Sgr;-&Dgr; modulator makes it possible to predict its transfer function and its encoding performance by assuming that the quantizer introduces an encoding error, the spectrum of which is that of decorrelated white noise for the input signal. With this assumption, the behaviour of the &Sgr;-&Dgr; modulator according to the simulation is predicted, except during the appearance of limit cycles.
It has not been possible to describe any device having the encoding of properties a digital to digital &Sgr;-&Dgr; modulator without the drawbacks of the existence of unpredictable limit cycles.
SUMMARY OF THE INVENTION
A first aspect of the invention relates to a modulator of the aforementioned type, in which the quantization interval of the quantizer is a prime number.
Thus, as will appear more clearly on reading the following description, this feature makes it possible to extend the duration of the output signal cycles as much as possible. It then follows that, since the energy of this signal is distributed over a larger number of lines, the latter are of lower power. The mechanisms leading to the appearance of limit cycles produce the latter with a decreased power (this phenomenon has been observed during simulation).
A second aspect of the invention relates to a digital frequency synthesizer comprising a phase-locked loop having a variable frequency divider in the feedback path, and further comprising a digital to digital &Sgr;-&Dgr; modulator according to the first aspect, in order to encode a signal for controlling the division ratio of the variable frequency divider.
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patent: 08 256061 (1996-10-01), None
Harris, F.;“A Modified Delta-Sigma Quantizer to Obtain High Resolution A/D Conversion with Small Excess Sample Rates”; Proceedings of the Asllomar Conference on Signals, Systems and Computers. Pacific Grove, Oct. 31—Nov. 2, 1988; New York, IEEE; vols. 1 & 2 Conf. 22; pp. 622-625; XP000130325.
Magrath, A. J., et al.; A Sigma-Delta Modulator Topology with High Linearity: Circuits and Systems, 1997: ISCAS '97: Proceedings of 1997 IEE International Symposium on Hong Kong Jun. 9-12, 1997: New York, pp. 53-56; XP010235973.
Camino Laurent
Level Philippe
Ramet Serge
Lauture Joseph
STMicroelectronics SA.
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