Digital-to-analogue converter circuits

Details Digital-to-analogue converter circuits Digital-to-analogue converter circuits

2002-05-24

2003-06-03

JeanPierre, Peguy (Department: 2838)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S144000

Reexamination Certificate

active

06573850

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters.
BACKGROUND TO THE INVENTION
Digital-analogue conversion based on converting a delta-sigma digital representation of a signal into an analogue waveform is now a commonplace technique. In a simple delta-sigma digital-to-analogue converter a string of pulses is generated, with a pulse density dependent upon the digital value to be converted, and low-pass filtered. The technique is prevalent in many high-volume application areas, for example digital audio, where several channels of high quality relatively low frequency (audio frequency) signals are required. High quality in this context typically implies −100 dB THD (Total Harmonic Distortion) and 100 dB SNR (Signal to Noise Ratio). However, in such high-volume markets manufacturing cost is also very important.
In general, a digital-to-analogue converter requires positive and negative reference voltages to define the amplitude of the output signal. A digital-to-analogue converter draws some current from these reference voltage ports, and this current will generally be signal dependent.
These reference voltages are typically generated from a source of low but non-zero output impedance, for example by a power supply or buffer with a decoupling capacitor. The source will have a finite ESR (Equivalent Series Resistance), and there will be additional resistance between the source, the decoupling and the device due to the effects of resistive PCB tracking, package lead resistance, and bond wire resistance.
The result is that any signal-dependent current drawn by the DAC from the references causes a signal-dependent voltage ripple to appear on the reference voltages actually applied to the DAC. Since the DAC output signal is proportional to the reference voltage, this multiplies the ideal digital-to-analogue converter output by this ripple. The consequent modulation of the output signal is apparent as signal distortion, for example, generating harmonic distortion components with a sine wave signal.
Furthermore in a stereo or multi-channel system it is often uneconomic to supply a digital-to-analogue converter for each channel with a separate voltage reference supply, or even separate decoupling, PCB traces, or integrated circuit pins. In these situations the reference ripple caused by one channel's DAC can appear on the reference voltage for other DACs, modulating the outputs of these other DACs as well as its own output.
This invention described herein is directed to digital-to-analogue converter circuits intended to reduce or eliminate signal dependent reference currents. A digital-to-analogue converter design for which the reference currents are substantially independent of output signal should be capable of lower distortion for a given source impedance. Alternatively, for a given acceptable level of performance, the digital-to-analogue converter should be more tolerant of source impedance, so allowing a design engineer to reduce costs by specifying fewer or cheaper, lower quality external components.
Many delta-sigma digital-to-analogue converters use switched-capacitor techniques.
FIG. 1
shows an example of a simple switched-capacitor DAC
100
suitable for use in a delta-sigma DAC system.
An operational amplifier
102
has a non-inverting input connected to a constant voltage V
mid
118
, typically ground. Operational amplifier
102
has an output
120
providing an output voltage V
out
and a feedback capacitor C
f
104
is connected between the output and an inverting input of the operational amplifier. A second capacitor C
2
106
is switchably connected across feedback capacitor
104
by means of switches
108
and
110
. Switch
108
allows one plate of capacitor
106
to be connected either to C
f
104
or to a positive reference voltage V
P
112
or a negative reference voltage V
N
114
. Switch
110
allows the other plate of capacitor
106
to be connected either to feedback capacitor
104
or to a second constant voltage, V
mid2
116
.
In operation switches
108
and
110
are controlled by a clock generator (not shown in
FIG. 1
) providing two clock phases Phi
1
200
and Phi
2
202
, as shown in FIG.
2
. Each of these clock signals comprises a charge phase
204
during which capacitor C
2
106
is charged and a dump phase
206
during which the charge on capacitor C
2
106
is shared with or dumped to the feedback capacitor C
f
104
. As can be seen from
FIG. 2
Phi
1
200
controls the charging phase and Phi
2
202
controls the dump phase.
In more detail, during the charging phase Phi
1
(
200
,
204
) capacitor C
2
is charged, with V
mid2
(generally the same voltage as V
mid
) applied to one terminal and V
P
or V
N
applied to the other terminal. Typically values of V
P
112
and V
N
114
are +3V and −3V respectively, with respect to V
mid
118
. The choice of V
P
or V
N
for any particular cycle is defined by a digital delta-sigma signal applied to switch
108
during this charging phase Phi
1
. During the dump phase, Phi
2
(
202
,
206
), C
2
is disconnected from V
P
, V
N
and V
mid2
and connected in parallel with the op amp feedback capacitor C
f
104
.
Typically C
2
106
is much smaller than the op amp feedback capacitor C
f
104
. The left-hand side of C
2
is switched between a voltage equal to V
mid
118
(since the inverting terminal of op amp
102
is a virtual earth, that is it is at substantially the same voltage as the non-inverting terminal) and V
mid2
. Assume for simplicity that as usual V
mid2
=V
mid
. Then if V
P
rather than V
N
is applied to the other end of C
2
during Phi
1
200
for many consecutive clock cycles, the output V
out
120
will converge to equal V
P
112
, to achieve a steady state in which both the left-hand side and the right-hand side of C
2
106
are switched between equal voltages each cycle. Similarly if V
N
114
is applied each cycle, V
out
will converge to V
N
114
. If V
P
and V
N
are each applied half the time, the output
120
will be the average of V
P
and V
N
. In general for a V
P
:V
N
duty cycle of m: (1−m), the steady-state output will be given by V
out
=m*V
P
+(1−m)*V
N
. In this context “duty cycle” should be understood as the fraction, proportion or ratio of the number of connections to V
P
to the number of connections to V
N
, for example measured in clock cycles.
The duty cycle is controlled by a digital delta-sigma signal to alternately connect C
2
106
to V
P
and V
N
to provide the required output voltage
120
. This output voltage
120
will vary from V
P
to V
N
according to the duty cycle applied. Thus, in effect, the DAC circuit may be considered as having a gain from the voltages (
112
and
114
) applied to the switched capacitor to the output
102
defined by (V
out,max
−V
out,min
)/(V
P
−V
N
) of substantially unity. The skilled person will recognise that the gain of circuit
100
may be adjusted, for example, by connecting a voltage divider to output
120
and taking the voltage for capacitor C
f
104
from a tap point on this divider, for example to provide a gain of 2. However typically the circuit will have a relatively low gain, for example less than 10 and more typically less than 3. This also applies to the DAC circuits which are described later.
The applicant has recognised that the above-described prior art DAC circuit suffers from a problem associated with signal-dependent loading of reference voltage sources for voltages V
P
112
and V
N
114
. The effects of signal-dependent loading of reference voltage supplies are known in the context of other circuits, but it has not previously been recognised that switched capacitor DAC circuits of the type shown in
FIG. 1
, in which a charge-sharing capacitor connected in parallel with a feedback capacitor is alternately connected to both positive and negative reference voltage sources, can

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