Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-04-02
2003-09-16
JeanGlaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06621440
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to digital to analogue converters (DACs) and more specifically to resistor ladder digital to analogue converters.
It is known in the art to use DACs for a wide variety of applications where a digital word needs to be converted to an analogue signal. The need for these devices is increasing greatly as we enter an increasingly digital age, where our music, television, movies and communications are digitally coded.
The basic resistor ladder form of DAC is shown in FIG.
1
. There are P−1 resistors connected in series between reference voltage sources Vref+ and Vref−. This divides the voltage into steps of (Vref+−Vref−)/P−1. There are P tap-off points inclusive of Vref+ and Vref−. Each of these tap-off points is connected to the analogue output Vout via a respective switch. The input digital word is decoded and used to close one of the switches. Hence the required output voltage is generated. The output voltage is buffered with a high impedance output stage
2
, so that the resistance of the switch causes no voltage drop.
This design is very wasteful as P becomes very large, in that a vast number of resistors and switches may be needed (a 20-bit DAC would need over 1 million resistors and switches). As is well known in the art, providing that P can be factorised to P=MN, it is possible to implement the same function using a lot fewer resistors and switches than the circuit in
FIG. 1
, by segmenting the resistor array into a number of stages.
For example, U.S. Pat. No. 5,495,245 describes a DAC wherein the resistor ladder has been segmented into two separate outer ladders and an inner ladder. Each outer ladder divides a full scale voltage and selects a tap in accordance with the most significant bits (MSBs) of the digital input word. Opposite ends of the inner ladder are connected to the selected tap points on the outer ladders, so that a voltage interval spanned by the inner ladder effectively slides up and down as the MSBs of the input signal vary. Switches on the inner ladder respond to the least significant bits (LSBs), to select the final output voltage, within the interval defined by the MSBs.
Other segmented DAC designs are known from U.S. Pat. Nos. 5,554,986 and 5,703,588. Various sources of error are known in such devices, arising from imperfect matching of resistor values, switch resistances, loading effects and so forth.
Loading of the outer resistor ladders by the second ladder in U.S. Pat. No. 5,495,245 is eliminated by allowing all the current in the two outer ladders to pass through the inner ladder. To work satisfactorily, this requires the inner ladder resistors to be scaled such that the total resistance of the inner ladder is equal to the resistance of a single resistor in the outer ladder. This has the disadvantage of a possible mismatch of resistor values, since matching is only readily achieved between resistors of identical value, or simple ratios. If the resistance is not exactly matched then an error occurs every time the inner ladder is moved.
Furthermore, in known designs some or all of the current flowing between Vref+ and Vref− must be diverted via the MSB switches to operate the inner ladder. Each switch has a non-zero resistance, which may vary from switch to switch in the same ladder and being in series between the outer and inner ladder. This leads to distortion in the matching between the inner ladder resistance and the resistance at each step if the outer ladder. Large switches will be required to keep this error down, which in effect will take up a lot of the area saved by segmenting in the first place.
SUMMARY OF THE INVENTION
The inventor has sought to provide an improved segmented ladder DAC design, which eliminates one or both these drawbacks. Independently, the inventor also seeks to provide DAC designs providing differential rather than single-ended outputs, without necessarily doubling the size of the circuit.
The invention in a first aspect provides a digital to analogue converter comprising at least first and second resistor ladders and at least first and second banks of switches, means for controlling said switches in accordance with at least the most significant bits of a digital input signal, first and second connecting means for connecting said first and second resistor ladders at their ends to form a ring topology, said first and second connecting means comprising means for deriving respective first and second analogue output signals to form a differential analogue output signal.
The invention in a second aspect of the invention provides a digital to analogue converter of segmented type, comprising at least first, second and third resistor ladders and at least first, second and third banks of switches, where the first two resistor ladders are connected in series by a load resistor and the third resistor ladder is connected across said load resistor, wherein a reference voltage source is connectable to selected points on each of the first and second resistor ladders via corresponding switches in the first and second banks of switches, said switches being selected in operation in accordance with the most significant bits of a digital input signal, and wherein an output is connectable to a selected point on the third resistor ladder via a corresponding switch in the third bank of switches, said switch being selected in operation in accordance with the least significant bits of said digital input signal.
The invention in a third aspect of the invention provides a digital to analogue converter comprising at least first and second resistor ladders and at least first and second banks of switches, means for controlling said switches in accordance with at least the most significant bits of a digital input signal, wherein each switch of the first and second banks of switches forms one of a matched pair of switches controlled to be closed and opened as a pair, the second switch in operation providing feedback to an amplifier such that a reference voltage can be imposed on the ladder independently of the resistance of the switches.
These and other optional features of the invention are defined in the appended claims. The three aspects of the invention may be applied independently of one another. The three aspects of the invention may also be used in any combination, as illustrated in the detailed description of the embodiments which follows.
REFERENCES:
patent: 4459580 (1984-07-01), Furukawa
patent: 4918448 (1990-04-01), Hauviller et al.
patent: 5093661 (1992-03-01), Tanimoto
patent: 5495245 (1996-02-01), Ashe
patent: 5534862 (1996-07-01), Gross et al.
patent: 5554986 (1996-09-01), Neidorff
patent: 5617091 (1997-04-01), Uda
patent: 5627537 (1997-05-01), Quinlan et al.
patent: 5648780 (1997-07-01), Neidorff
patent: 5703588 (1997-12-01), Rivoir et al.
patent: 5714953 (1998-02-01), Mitani et al.
patent: 5831566 (1998-11-01), Ginetti
patent: 5838273 (1998-11-01), Sauerbrey et al.
patent: 5969657 (1999-10-01), Dempsey et al.
patent: 5969658 (1999-10-01), Naylor
patent: 5977898 (1999-11-01), Ling et al.
patent: 5999115 (1999-12-01), Connell et al.
patent: 10004354 (1998-01-01), None
Biren Steven R.
JeanGlaude Jean Bruner
Koninklijke Philips Electronics , N.V.
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