Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-11-21
2003-04-01
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C333S018000, C327S395000
Reexamination Certificate
active
06542099
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a digital to analog interface with equalized total signal delay and a method of constructing it.
BACKGROUND OF THE INVENTION
Digital to analog converters (DAC's) have a plurality of unit cells for converting the digital input to an analog output in a timed operation directed by a clock input. Each cell typically has a data input circuit responsive to the clock input and digital data input and an analog output circuit responsive to the data input circuit to generate the analog output. There is a propagation delay as the analog output network sums the analog outputs of the analog output circuits tapped into it. These delays are generally uniform but they cause noise and distortion in the signal provided to the termination load. Additional noise and distortion occurs because of the delays from cell to cell, which are uniform, as the clock input propagates along the clock input distribution network. This latter error source at the clock input has been addressed by using a binary tree network input so that all clock inputs are delayed by the same amount to each cell. But this approach requires additional area and conductors on the chip which is not desirable. The former error source at the analog output has not been satisfactorily addressed. Simply adding a binary tree network here at the analog output mirroring the binary tree at the clock input is not acceptable because the area around the output is already dedicated to other necessary circuitry. Further, in some DAC's the current output is high and would require substantial size conductors to construct the binary tree.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide an improved digital to analog interface with equalized total signal delay and a method of constructing it.
It is a further object of this invention to provide such an improved digital to analog interface which eliminates the need for a binary tree at the clock input.
It is a further object of this invention to provide such an improved digital to analog interface which addresses the noise and distortion introduced at the analog output as well as the clock input.
It is a further object of this invention to provide such an improved digital to analog interface which is simple and requires very little additional area and not in the primary clock input area.
This invention results from the realization that a truly simpler and more effective digital to analog interface which addresses both clock input and analog output generated noise and distortion can be made by adding a termination on the clock input distribution network which turns it into a transmission line and enables the propagation delays of the clock input distribution network to be matched to that of the analog output network and its termination load so that the clock input and analog output delays are synchronized resulting in an equalized total signal delay across all of the unit cells of the interface.
This invention features a digital to analog interface with equalized total signal delay including a plurality of unit digital to analog converter cells each having a clock input and an analog output. A clock input distribution network propagates a clock input through the unit cells tapped along the distribution network. An analog output network sums the analog outputs from each unit cell and propagates the sum signal along the network to a first termination. The analog outputs being delayed from cell to cell by a first predetermined interval defined by the combination of the analog output network and the first termination. There is a second termination connected to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock inputs to the unit cells equal to the first predetermined time interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.
The invention also features a method of equalizing total signal delay across a digital to analog interface including constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output. An analog output network is constructed for summing the analog outputs for delivery to a first termination which in combination with the analog output network defines a first predetermined time delay between the unit cells. A clock input distribution network is constructed for propagating a clock input to each of the unit cells tapped along the clock input distribution network. A second termination is connected to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock inputs to the unit cells equal to the first predetermined interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.
REFERENCES:
patent: 5086271 (1992-02-01), Haill et al.
patent: 5661427 (1997-08-01), McBride et al.
patent: 6219384 (2001-04-01), Kliza et al.
patent: 6285723 (2001-09-01), Yamada et al.
Mercer Douglas A.
Schofield William G. J.
Analog Devices Inc.
Iandiorio & Teska
Rosenholm R. Stephen
Teska Kirk
Williams Howard L.
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