Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-12-18
2003-04-15
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06549157
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital-to-analog converting device and method, and more particular to a digital-to-analog converting device and method operating under two clock signals of different periods. For example, the device and the method can be used with reduced jitter in waveform pulse generated by the HomePNA 1.0/2.0 compliant modules, and any other digital communication systems that utilize pre-synthesized waveforms as sources for generating transmitted signals.
BACKGROUND OF THE INVENTION
Clock jitter is always an important issue in a communication system. A large clock jitter inherent in signal transmission may seriously degrade system performance. In the international Home Networking standard HomePNA 1.0, for example, information is carried by signals transmitted and processed in sequence. Therefore, the permissive range of a clock jitter is highly restricted in Home Networking environment.
In a HomePNA 2.0 compliant system, it should be backward compatible with the HomePNA 1.0 system. Therefore, a HomePNA 1.0 compliant module is generally included in a HomePNA 2.0 compliant modem, and the clock frequency of a digital-to-analog converter (DAC) of the system is selected to meet both timing or clock frequency requirements in HomePNA 1.0 as well as in HomePNA 2.0 under the constraints of hardware complexity and system performance.
The DAC clock frequency selected mainly for HomePNA 2.0 applications, unfortunately, is not an integer multiple of the system clock frequency of the HomePNA 1.0 module. Hence, each waveform pulse transmitted by the HomePNA 1.0 module and output through the DAC circuit shall drift from its desired timing due to the frequency difference in these two clock domains. Timing accuracy requirement of the transmitted waveform is, therefore, violated as if the system master clock had a big jitter.
To achieve jitter reduction, two possible approaches have been suggested as follows:
1. Double the DAC clock frequency and pre-filter signal waveform samples; and
2. Double the DAC clock frequency and implement an analog filter in the analog front-end circuit to perform filtering on a set of square waveform driven by a system clock.
Both above conventional approaches will reduce the jitter to half of its original design. However, these methods need either a DAC circuit that performs the digital-to-analog conversion at a double speed or an analog filter in the analog front-end to smooth a raw digital square waveform that is clocked to the DAC circuit at the same double speed. The later complicates the analog front-end circuit design since an analog filter is required.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a digital-to-analog converting device and method for reducing clock jitter in a digital communication system, which need only a half of DAC clock frequency as compared with that in either of the conventional approaches to achieve the same jitter performance.
Another object of the present invention is to provide a digital-to-analog converting device and method for reducing clock jitter in a digital communication system, which involve in a reduced clock jitter without significantly increasing the complexity of the circuit, and thus be cost-efficient.
A first aspect of the present invention relates to a digital-to-analog converter for generating an analog signal in response to a first clock signal having a first period and a second clock signal having a second period. The converter includes a phase monitor generating an index signal according to a phase relationship between the first and the second clock signals; a first waveform sample table storing therein a first set of waveform samples, and enabled by the first clock signal to sequentially output the first set of waveform samples in response to a series of triggering of the second clock signal; a second waveform sample table storing therein a second set of waveform samples, and enabled by the first clock signal to sequentially output the second set of waveform samples in response to a series of triggering of the second clock signal, wherein the second set of waveform samples has a delay time less than the second period from the first set of waveform samples; a multiplexer electrically connected to the phase monitor, and the first and second waveform sample tables for permitting one of the first and second sets of waveform samples to be outputted in response to the index signal; and a digital-to-analog circuit electrically connected to the multiplexer for converting the waveform samples outputted through the multiplexer into an analog signal.
The converter can be used in a digital communication system in which the first period is a non-integer multiple of the second period.
Preferably, the delay time between the first and second sets of waveform samples is equal to a half of the second period.
A second aspect of the present invention relates to a digital-to-analog converter for generating an analog signal in response to a first clock signal having a first period T
A
and a second clock signal having a second period T
B
. The converter includes a phase monitor generating an index signal according to a phase relationship between the first and the second clock signals; a plurality of waveform sample tables storing therein a plurality of sets of waveform samples, respectively, each of which is enabled by the first clock signal to sequentially output the set of waveform samples in response to a series of triggering of the second clock signal, wherein a delay time is present between every two adjacent sets of waveform samples, and an overall delay time between the earliest and the latest sets of waveform samples is less than the second period; a multiplexer electrically connected to the phase monitor, and the plurality of waveform sample tables for permitting one of the plurality of sets of waveform samples to be outputted in response to the index signal; and a digital-to-analog circuit electrically connected to the multiplexer for converting the waveform samples outputted through the multiplexer into an analog signal.
For a digital communication system in which the first period is a non-integer multiple of the second period, it is given that n
A
*T
A
=n
B
*T
B
in which n
A
and n
B
are positive integers, and the converter preferably includes n
A
waveform sample tables.
A third aspect of the present invention relates to a method for converting a digital signal into an analog signal in response to a first clock signal having a first period and a second clock signal having a second period. The method includes steps of monitoring a phase relationship between the first and second clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and converting one of the plurality of pre-stored sets of waveform samples into an analog signal to be outputted according to the phase relationship.
In an embodiment, two series of waveform sample are pre-stored for being optionally converted into the analog signal. Preferably, a second series of waveform samples has a delayed phase relevant to a half of the second period from a first series of waveform samples. The second series of waveform samples is selected to be converted into the analog signal in a case that the transmission is started between a rising edge and the following falling edge of the second clock signal, and the first series of waveform samples is selected to be converted into the analog signal in a case that the transmission is started between a falling edge and the following rising edge of the second clock signal.
REFERENCES:
patent: 5574455 (1996-11-01), Hori et al.
patent: 5880689 (1999-03-01), Kushner
patent: 2001/0019313 (2001-09-01), Takahashi et al.
Chen Min-Chieh
Liu Shuenn-Ren
Tseng Yang-Chung
Tzou Ching-Kae
Yin Shih-Chung
Lowe Hauptman & Gilman & Berner LLP
Silicon Integrated Systems Corp.
Williams Howard L.
LandOfFree
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