Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-05-27
2001-12-11
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000, C341S153000, C341S154000
Reexamination Certificate
active
06329941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC having a partially segmented sub-DAC.
2. Background of the Invention
Digital-to-analog conversion is the process of converting a signal in digital form into a signal in analog form. Digital-to-analog converters (DACs) typically convert a digital code to an analog voltage by assigning a voltage weight or current weight to each bit in the digital code and summing the voltage or current weights corresponding to each of the bits of the digital code.
There are two types of DACS, binary weighted DACs and segmented DACs. Binary weighted DACs are typically implemented as a network of resistors and switches which are selectively activated by the bits of the digital code so as to selectively accumulate a series of currents which are summed by an amplifying circuit. Purely binary weighted DACs generally are not used in high performance applications due to relatively high process variations between the resistors in the resistor network and particularly to the difficulty in proportionally matching resistors of substantially vastly different sizes in the resistor network.
Segmented DACs are an attempt to improve the performance over purely binary weighted DACs. In general terms, a segmented DAC converts the digital input code into a plurality of signals which drive equally weighted current sources.
There are known DACs which combine binary weighted and segmented architectures. For example, a 12-bit partially segmented DAC, i.e., a DAC which is partitioned such that a first DAC portion is segmented and a second DAC portion is binary weighted, is disclosed in “An Inherently Monotonic 12 Bit DAC” by John Schoeff, IEEE Journal of Solid State Circuits, vol. 14. no. 6 (December 1979) and incorporated herein by reference. The three most significant bits (MSBs) of the digital input word are input to an eight segment sub-DAC which is capable of generating any of eight coarse current levels. The nine least significant bits (LSBs) of the digital input word are fed to a binary weighted sub-DAC which is capable of generating any of
512
distinct fine current levels within each of the eight coarse current levels.
A second partially segmented DAC is described in “A Low Power Stereo 16-bit CMOS D/A Converter for Digital Audio” by Hans Schouwenaars et al., IEEE Journal of Solid State Circuits, vol. 23, no. 6 (December 1988). This 16-bit DAC includes a segmented sub-DAC having a plurality of equally-sized coarse current sources which are applied to a set of three-way current switches. A decoder transforms the binary input code of the 6 MSBs into a thermometer code which controls the coarse current switches. One of the coarse current sources is connected by the three-way switches to a divider stage which divides the applied current into binary weighted fine current levels. The fine binary-weighted currents, generated by a binary weighted sub-DAC corresponding to the 10 LSBs of the digital input code, are switched to the output by two-way current switches controlled thereby. The coarse and fine currents are summed and converted into a voltage by an amplifying circuit.
Although segmented DACs typically have improved linearity with respect to DACs having binary weighted architectures, segmented DACs nevertheless often fail to achieve the linearity requirements demanded by today's high performance applications. Calibration techniques thus exist for improving the performance of segmented DACs, such as improving the linearity thereof.
One calibration technique in DAC designs is laser trimming which more closely matches resistor values in a DAC so as to improve the linearity thereof. Another calibration technique is self-calibration in which a plurality of stored charges which control the operating characteristics of the current sources within a DAC are periodically calibrated to ensure that current levels generated by the current sources are equally or proportionally matched to each other. One such self-calibration technique, described in “A Self-Calibration Technique for Monolithic High Resolution D/A Converters”, by D. Wouter J. Groeneveld et al., IEEE Journal of Solid State Circuits, vol. 24, no. 6 (December 1989) and incorporated herein by reference, utilizes N+1 equally-sized current sources for generating N useable current sources. Specifically, the technique includes a serial shift register which sequentially calibrates the current sources of the DAC. The current sources which are not being calibrated are enabled to form the current sources of a segmented sub-DAC of the 16-bit DAC. The current source which is being calibrated is shifted out of the DAC so that it is unusable. By sequentially disabling a current source for calibration while the remaining current sources remain enabled to perform a conversion operation, no calibration time is necessary.
Despite the performance gains achieved by the above-identified DAC architectures, there exists a need for a DAC having improved linearity, high dynamic range and reduced power and size.
SUMMARY OF THE INVENTION
The present invention overcomes limitations and shortcomings of existing DAC designs and satisfies a significant need for a DAC which provides an improved performance. The DAC, according to the present invention, includes a first sub-DAC having a segmented architecture, including equally-sized current sources and current switches connected thereto which are controlled by a decoded version of the MSBs of the digital input signal. With the first sub-DAC being fed by, for example, the first four MSBs of the digital input signal, the first sub-DAC can generate any of 16 coarse current levels.
The first sub-DAC preferably is also a trimmable DAC by including self-calibration circuitry so that the equally-sized current sources are calibrated to closely match each other. The self-calibration circuitry includes a cyclic serial shift register which sequentially disables a single current source for calibration while the remaining current sources which are not disabled remain available for performing a conversion operation.
The DAC, according to the present invention, further includes a second sub-DAC which is capable of generating any of a number of fine current levels between successive coarse current levels generated by the first sub-DAC. The second sub-DAC preferably is itself partially segmented, including a plurality of equally-sized current sources whose currents are selectively steered and accumulated by the MSBs of the digital input signal which are not input to the first sub-DAC. The second sub-DAC further includes a binary-weighted current divider which is controlled by the LSBs of the digital input signal of the DAC. The current output levels from the first sub-DAC and the second sub-DAC are added together by an amplifying circuit to generate an output voltage signal which is an analog version of the digital input signal of the DAC.
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Jorgenson Lisa K.
Paik Steven S.
STMicroelectronics Inc.
Szuwalski Andre
Tokar Michael
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