Digital-to-analog converting circuit giving linear relation...

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

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Details

C341S138000

Reexamination Certificate

active

06608579

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a DAC circuit (Digital-to-Analog converting circuit).
2. Description of Related Art
FIG. 12
is a circuit diagram of a ring oscillator using a conventional DAC circuit, and in the figure, reference numeral
1
signifies the DAC circuit that outputs analog currents Idac
1
and Idac
2
according to digital codes into two split routes.
Reference numerals
2
a
to
2
d
signify a differential amplifier connected in a ring, and
3
signifies a composite circuit composed of two differential amplifiers, which outputs a signal voltage obtained by adjusting the ratio of a signal voltage from the differential amplifier
2
b
to a signal voltage from the differential amplifier
2
d
in accordance with the analog currents Idac
1
and Idac
2
and thereafter adding the outputs of the above two differential amplifiers. The differential amplifiers
2
a,
2
b,
and one of the differential amplifiers inside the composite circuit
3
constitute a three-stage ring oscillator; and the differential amplifiers
2
a
to
2
d
and the another differential amplifier inside the composite circuit
3
constitute a five-stage ring oscillator.
In addition, in the DAC circuit
1
, reference numeral
11
denotes a p-channel FET having a source connected to a power supply VCC and having a drain connected to a constant current source
12
,
13
to
16
each denote the p-channel FET having each source connected to the power supply VCC and having each gate connected commonly to a gate of the p-channel FET
11
, and each p-channel FET constitutes a current mirror circuit together with the p-channel FET
11
. These p-channel FETs
13
to
16
are provided in correspondence with each bit of input digital codes. For example, when the input digital codes are 4 bits in total, namely, from bit
0
to bit
3
, the DAC circuit
1
includes four p-channel FETs
13
to
16
, as shown in FIG.
12
. Further, with regard to the p-channel FETs
13
to
16
, the transistor number (transistor size) is produced in correspondence with the corresponding bit thereof. For example, if the transistor number of the p-channel FET
16
corresponding to bit
0
is assumed to be Scale=1, the transistor number of the p-channel FET
15
corresponding to bit
1
is produced in Scale=2, the transistor number of the p-channel FET
14
corresponding to bit
2
is produced in Scale=4, and the transistor number of the p-channel FET
13
corresponding to bit
3
is produced in Scale=8, and further the transistor number of the p-channel FET
11
of the current mirror circuit source is produced in Scale=50.
Reference numerals
17
to
20
each denote a switch that switches the analog current from the corresponding drain of the p-channel FETs
13
to
16
in correspondence with the input digital code between two routes of analog currents Idac
1
and Idac
2
, which are supplied to the composite circuit
3
.
FIG. 13
is a table chart of the relation between the digital codes and the analog currents Idac
1
, Idac
2
of the conventional DAC circuit.
FIG. 14
includes a characteristic chart of the relation between the digital codes and the analog currents Idac
1
, Idac
2
of the conventional DAC circuit, and a characteristic chart of the relation between the digital codes and the oscillation frequency of the ring oscillator using the DAC circuit of the same.
FIG. 15
includes a characteristic chart of the relation between the digital codes and the analog currents Idac
1
, Idac
2
of an ideal DAC circuit, and a characteristic chart of the relation between the digital codes and the oscillation frequency of the ring oscillator using the DAC circuit of the same.
Next, the operation will be explained.
In the DAC circuit
1
, the p-channel FET
11
of the current mirror circuit source connected to the constant current source
12
has the transistor number produced in Scale=50, 50 &mgr;A constantly flowing through the p-channel FET
11
.
In the p-channel FETs
13
to
16
connected in the current mirror connection configuration with the p-channel FET
11
, a constant current according to each transistor number flows through the corresponding transistor. That is, the transistor number of the p-channel FET
13
is Scale=8, 8 &mgr;A constantly flowing through the p-channel FET
13
; the transistor number of the p-channel FET
14
is Scale=4, 4 &mgr;A constantly flowing through the p-channel FET
14
; the transistor number of the p-channel FET
15
is Scale=2, 2 &mgr;A constantly flowing through the p-channel FET
15
; and the transistor number of the p-channel FET
16
is Scale=1, 1 &mgr;A constantly flowing through the p-channel FET
16
.
The switches
17
to
20
switch the analog currents from the drains of the p-channel FETs
13
to
16
, respectively, in correspondence with the input digital codes. For example, if the digital code is “0”, the side of the analog current Idac
2
will be selected; if the digital code is “1”, the side of the analog current Idac
1
will be selected.
FIG. 13
illustrates the relation between the digital codes and the analog currents Idac
1
, Idac
2
in that case. Thus, the analog currents Idac
1
, Idac
2
produced by the DAC circuit
1
varies uniformly in accordance with the digital codes, and variations in the analog currents Idac
1
, Idac
2
for the 1 LSB of the digital codes is constant relative to all the values of the digital codes.
In the ring oscillator, the differential amplifiers
2
a,
2
b,
and one of the differential amplifiers inside the composite circuit
3
constitute the three-stage ring oscillator that generates higher frequencies; and the differential amplifiers
2
a
to
2
d
and the other inside the composite circuit
3
constitute the five-stage ring oscillator that generates lower frequencies.
The composite circuit
3
adjusts the ratio of a signal voltage from the differential amplifier
2
b
to a signal voltage from the differential amplifier
2
d
in accordance with the analog currents Idac
1
and Idac
2
supplied from the DAC circuit
1
, thereafter adds the outputs of the above two differential amplifiers, and outputs the result as a signal voltage. For instance, if the analog current Idac
1
is 0 &mgr;A and the analog current Idac
2
is 15 &mgr;A, the composite circuit
3
will output a signal voltage acquired by decreasing the weighting of the signal voltage from the differential amplifier
2
b
and increasing the weighting of the signal voltage from the differential amplifier
2
d
and then adding both the results; and if the analog current Idac
1
is 15 &mgr;A and the analog current Idac
2
is 0 &mgr;A, the composite circuit
3
will output a signal voltage acquired by increasing the weighting of the signal voltage from the differential amplifier
2
b
and decreasing the weighting of the signal voltage from the differential amplifier
2
d
and then adding both the results.
The left characteristic chart in
FIG. 14
illustrates the relation between the digital codes and the analog currents Idac
1
, Idac
2
of the DAC circuit
1
illustrated in
FIG. 12
, which is a graphic expression of the table illustrated in FIG.
13
. The right characteristic chart in
FIG. 14
illustrates the relation between the digital codes input to the DAC circuit
1
and the oscillation frequency output from the composite circuit
3
, when the ring oscillator is controlled using the analog currents Idac
1
, Idac
2
according to the digital codes.
Since the conventional DAC circuit is configured as above, the analog currents Idac
1
, Idac
2
produced by the DAC circuit
1
varies uniformly in accordance with the digital codes, and the variations in the analog currents Idac
1
, Idac
2
for the 1 LSB of the digital codes is constant relative to all the values of the digital codes.
However, when the oscillation frequency of the ring oscillator is controlled using the analog currents Idac
1
, Idac
2
, the oscillation frequency of the ring osci

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