Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-10-21
2002-01-08
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S118000
Reexamination Certificate
active
06337646
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital-to-analog converter and a digital-to-analog converting method, and more particularly, it relates to a digital-to-analog converter and a digital-to-analog converting method in which a nonlinear error of an analog output resulting from digital-to-analog conversion (D/A conversion) is decreased without using any specific analog process.
BACKGROUND OF THE INVENTION
With recent high integration of large scale integrated circuits (herein after referred to as LSIs), there are increasing demands for LSIs mounting both analog circuits and digital circuits. A high-accuracy and low-cost digital-to-analog converter (hereinafter referred to as a D/A converter) and a high-accuracy and low-cost analog-to-digital converter (hereinafter referred to as an A/D converter) are required to be mounted on such LSIs. Therefore, it is significant to realize a high-accuracy analog circuit by using a general semiconductor process without using a high-accuracy but high-priced analog process.
As an example of a D/A converter, an n-bit D/A converter
80
using a ladder circuit (R-2R resistance net)
82
is shown in FIG.
7
. The D/A converter
80
of the R-2R resistance net comprises the ladder circuit
82
and a switch controller
84
. The ladder circuit
82
comprises a resistance net of resistors R and 2R, and n (which is an integer) analog switches S (Sn, Sn-
1
, Sn-
2
, . . . , S
4
, S
3
, S
2
and S
1
). The switches S (Sn, Sn-
1
, Sn-
2
, . . . , S
4
, S
3
, S
2
and S
1
) are connected to the switch controller
84
respectively through control wires W (Wn, Wn-
1
, Wn-
2
, . . . , W
4
, W
3
, W
2
and W
1
).
The switches Sn, Sn-
1
, Sn-
2
, . . . , S
4
, S
3
, S
2
and S
1
correspond respectively to bits Dn, Dn-
1
, Dn-
2
, . . . , D
4
, D
3
, D
2
and D
1
of an n-bit digital input signal D (i.e., “Dn Dn-
1
Dn-
2
. . . D
4
D
3
D
2
D
1
”) input to the switch controller
84
. Under control of the switch controller
84
, when a bit Dk (wherein k is an integer of 1 to n) of the input signal D is “1”, the switch Sk corresponding to the bit Dk is switched to a voltage Vref, and when the bit Dk is “0”, the switch Sk corresponding to the bit Dk is switched to a ground. In this manner, the switches S are switched in accordance with the input signal D so as to adjust a voltage applied to the ladder circuit
82
. Thus, the D/A converter
80
can output an analog signal (namely, an output voltage Vout) in accordance with the input digital signal D.
Since this R-2R resistance net
82
includes two types of resistors R and 2R (it includes one type when two resistors R are connected in series to form a resistor 2R). Therefore, the circuit can be constructed by using the resistors each having the same accuracy and temperature coefficient. Furthermore, a high-accuracy D/A converter can be achieved by securing comparative precision of the respective resistors not by securing the absolute precision of each resistor. Accordingly, it can be considered that a high-accuracy D/A converter can be achieved by using resistors of uniform properties.
However, when resistors have voltage dependence, problems will arise even if the resistors of uniform properties are used. For example, in the case where the R-2R resistance net is formed by using a semiconductor process in which no high-accuracy resistance element is particularly used, the resistance element is often formed in an n-type diffused layer. However, depending on a voltage applied to the resistors, a depletion layer formed between the resistor and a p-type substrate is changed, so that the resistance value can be varied. When the resistance value is thus varied by the voltage applied to the resistor, it is difficult to achieve a high-accuracy D/A converter.
For example,
FIG. 8
is a simplified circuit diagram of a 2-bit D/A converter (including a ladder circuit)
90
, which corresponds to the case where n is 2 in the ladder circuit
82
(of the converter
80
) of FIG.
7
. In
FIG. 8
, resistors r
2
and r
1
each have the same properties and an uniform resistance value of 2R through the application of no voltage. In this circuit
90
, switches not shown (corresponding to the switches S
1
and S
2
of
FIG. 7
) are switched in accordance with an input signal “D
2
D
1
” so that voltages V
2
and V
1
applied to the resistors r
2
and r
1
can be varied as shown in TABLE 1 below.
TABLE 1
D2
D1
V2
V1
r2
rl
0
0
0
0
2R
2R
0
1
0
Vref
2R
2R + &Dgr;R
1
0
Vref
0
2R + &Dgr;R
2R
1
1
Vref
Vref
2R + &Dgr;R
2R + &Dgr;R
As shown in TABLE 1, since the resistors r
1
and r
2
have a voltage dependence, the resistors r
1
and r
2
each have the resistance value 2R when no voltage is applied. However, when a voltage Vref is applied, the resistance value is increased, for example, by &Dgr;R to be 2R+&Dgr;. In this manner, even when the resistors have the same properties, their resistance values are varied depending on whether or not a voltage is applied. Therefore, since the properties of the resistors are changed due to increase in an error of the resistance value, the conversion accuracy of the converter is degraded.
FIG. 9
shows a relationship between an error &Dgr;V (=Vout−Vr) generated between an analog output voltage Vout and an ideal voltage Vr and a digital input signal D (which is shown in a range from 0 (zero) to FS (full scale)) in a 10-bit D/A converter using such voltage-dependent resistors in a ladder circuit. The ideal voltage Vr is increased by a predetermined voltage with an increase of a least significant bit (LSB) of the input signal D, and a relationship between the input signal D and the ideal output voltage Vr is substantially linearly varied. In
FIG. 9
, assuming that the error is substantially zero when the input signal D is 0 and FS, the error &Dgr;V from the ideal output line (nonlinear error) reaches to the maximum error &Dgr;V_max in the vicinity of ½FS. This maximum error &Dgr;V_max largely affects the conversion accuracy of the D/A converter.
Thus, there is a need for a high-accuracy D/A converter and a high-accuracy D/A converting method in which a nonlinear error caused by a voltage dependence of a resistance element that degrades the accuracy of a D/A conversion can be corrected without using any specific analog process.
SUMMARY OF THE INVENTION
In the D/A converter of the present invention, an error (nonlinear error) between the output voltage of the D/A converter and an ideal output voltage can be corrected by using a correction signal generated by a correction circuit. By using the D/A converting method of the present invention capable of correcting the output voltage by using the correction signal, a high-accuracy and low-cost D/A converter can be realized without using any specific analog process.
The D/A converter of the present invention is characterized by comprising correction signal generating means for generating an m-bit digital correction signal (wherein m is a positive integer) in accordance with an n-bit digital input signal (wherein n is a positive integer of 2 or more); and digital-to-analog conversion means for converting an (n+m)-bit digital signal consisting of the n-bit input signal and the m-bit correction signal into an analog signal.
The D/A converting method of the present invention is characterized by comprising: a correction signal generating step of generating an m-bit digital correction signal (wherein m is a positive integer) in accordance with an n-bit digital input signal (wherein n is a positive integer of 2 or more); and an (n+m)-bit digital-to-analog converting step of converting an (n+m)-bit digital signal consisting of the n-bit digital input signal and the m-bit digital correction signal into an analog signal.
REFERENCES:
patent: 5153592 (1992-10-01), Fairchild et al.
patent: 5703586 (1997-12-01), Tucholski
patent: 6154158 (2000-11-01), Walker
patent: 6191715 (2001-02-01), Fowers
patent: 6278391 (2001-08-01), Walker
Hatani Naohisa
Ohkubo Manabu
Capella Steven
Wamsley Patrick
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