Digital-to-analog converter with high-speed output

Details Digital-to-analog converter with high-speed output Digital-to-analog converter with high-speed output

2000-05-25

2001-10-02

Lam, Tuan T. (Department: 2816)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S153000

Reexamination Certificate

active

06297759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital-to-analog converters (DAC's) and more particularly to high-speed, high-resolution, monolithic, integrated circuit (IC) digital-to-analog converters.
2. Description of the Related Art
Changes in the digital input code to a digital-to-analog converter (DAC) produce changes in the analog output that are often accompanied by output voltage spikes known as “glitches”. Each such glitch represents a conversion error because the output signal does not correspond exactly to the digital input signal. It is therefore an obvious goal of DAC design to reduce the occurrence or at least the effect of such glitches. Consequently, much effort and money has been devoted to finding a solution to the problem of overcoming glitch problems in DAC's. Indeed, the need for a solution becomes more and more acute as the bandwidth and transmission rates of data in telecommunications systems rapidly increase, thus requiring even greater DAC conversion speed and resolution.
One way to reduce the peak amplitude of these output spikes is to use lowpass filtering. One problem with this known solution, however, is that the energy contributed by the spikes then generally results in output non-linearity. In binary-coded DAC's, such as the one disclosed in U.S. Pat. No. 4,366,439 (Yamakito), or in &mgr;-law, PCM-coded DAC's such as is described in U.S. Pat. No. 4,369,433 (Yamakito), significant glitches occur even with small changes in the input signal when capacitors of large value are switched out and smaller capacitors are switched in.
Early work in low-glitch DAC technology focused on the development of “glitch free” decoders. DAC's constructed using these elements employed a new type of decoder which, for a unit increase in the value of the input code (one integer), turned on or off only one weighting element at a time. This kind of decoder became commonly known as a “thermometer decoder”. Such thermometer decoders were usually connected to an output network consisting of elements of equal strength or “weight”. A small change in the input code would then produce a uniform change in the output current or voltage both near and far from mid-scale values.
Although the glitch energy in a DAC using a thermometer-decoder is low, one weighting element must be used for each non-zero input code. For example, a DAC with a binary full-scale input of 2
14
requires over 8,000 weighting elements. In monolithic IC construction, DAC weighting networks with 256 elements are practical, but an 8,000-element array would require such a large amount of available silicon area as to be unacceptable.
The usual approach to high-resolution converter design is then to split the device's weighting elements into at least two sections, or segments. In these segmented designs, the higher strength weighting elements are driven by the most-significant bits (MSB's) in the input code, and the lower strength weighting elements are driven by the least-significant bits (LSB's). One might say that the higher strength weighting elements reside in the upper or MSB segment of the DAC, while the weaker elements reside in the lower or LSB segment.
One disadvantage of this MSB/LSB segmented design is that the “glitch-free” converter architectures found in the prior art typically reduce glitch energy only in single-segment converters—they do not guarantee glitch-free performance when applied to two or more segments of the same converter. More specifically, timing mismatches between the upper and lower segment decoders may themselves cause output glitches. For example, when the upper segment output increases by only one weighting element in response to a small code change, the lower segment may decrease by several element outputs.
The use of thermometer codes does, however, have advantages other than the production of low glitch energy. For example, because only one weighting element output at a time need typically be switched in as the digital input changes, the differential linearity of such a converter is better than that of a simple binary coded converter near mid-scale. Accordingly, the common practice is to design the converter with a thermometer-coded upper segment, but with a binary-coded lower segment. One example of this design is found in U.S. Pat. No. 4,665,380 (Lewyn). When such a converter is used for high-resolution audio disc reproduction, a sample-and-hold (S/H) circuit is typically included after the DAC analog output in order to hold the sample and hold input voltage at the end of the input sampling interval, thereby preventing the glitch present at the beginning of the next interval from passing through to the output.
An obvious drawback of including sample-and-hold circuits is that they, too, require additional circuit area and power. Furthermore, S/H circuits often introduce undesirable non-linearities, particularly when operated at high frequencies. Such non-linearities result from a variety of sources, which include amplifier slew-rate limitations when the output is transitioning from a currently held output voltage to the following one. Other high-speed sample-and-hold non-linearities arise from non-linear clock and input signal feedthrough. Still other non-linearities arise when the MOS switch resistance varies with output signal voltage and polarity.
Because DAC glitches have one-half of a clock cycle to settle out when used as a component within an analog-to-digital converter (ADC), the DAC of U.S. Pat. No. 4,665,380 (Lewyn) was suitable for use even without a sample-and-hold in an ADC. Even in such an application, however, the combination of series switches used in the MSB capacitor arrays to couple the MSB to the LSB array results in a significant amount of glitch energy, from which the system must recover within one-half clock cycle. An improvement that reduces the number of series switches in a thermometer coded DAC for use in an ADC is disclosed in U.S. Pat. No. 5,640,162 (Lewyn). However, even in this improved design, the series combination of switches used in the MSB capacitor arrays, as well as the timing mismatches between the upper- and lower-segment decoding blocks, results in glitch energy that is still too large for use in a high-resolution DAC that lacks a sample-and-hold circuit.
When it comes to a DAC that is divided into MSB and LSB segments, what is needed is therefore a topology that achieves lower glitch energy, preferably with even higher resolution, than is possible using existing designs. This invention provides such a topology.
SUMMARY OF THE INVENTION
The invention provides a digital-to-analog converter (DAC) that converts a digital input word into a corresponding analog output signal. The DAC according to the invention includes a capacitive digital-to-analog converter (CDAC) voltage reference source, which provides a plurality of CDAC reference voltages, and a CDAC segment, which includes a plurality of CDAC switches. Each CDAC switch has a plurality of CDAC switch states, in each of which the respective CDAC switch connects a respective one of the reference voltages, through a respective CDAC unit output capacitor, to a DAC output.
The DAC according to the invention also includes at least one resistive converter (RDAC) segment that includes an RDAC voltage reference source, which comprises an equally spaced resistive divider that provides a plurality of RDAC reference voltages, and first and second RDAC output buses. The RDAC segment also includes a first and a second plurality of RDAC switches. Each RDAC switch has a conductive state, in which it connects a respective one of the RDAC reference voltages to the first and second DAC output buses, respectively, and a non-conductive state, in which it isolates the respective RDAC reference voltage from the first and second RDAC output buses.
A bus selector arrangement is also included and has a first state, in which the first RDAC output bus is connected, via an RDAC output capacitor, to the DAC output, and a second state, in wh

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