Digital to analog converter with compensation memory addressed b

Details Digital to analog converter with compensation memory addressed b Digital to analog converter with compensation memory addressed b

1989-10-23

1990-10-16

Shoop, Jr., William M.

Coded data generation or conversion

Converter compensation

341145, H03M 106

Patent

active

049638700

ABSTRACT:
A digital/analog converting device comprises a first digital/analog converter for converting upper M bits of an input digital signal into a first analog signal; a memory for receiving, as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output-approximate data of S (S>N) bits in response to the address data; a second digital/analog converter for converting digital data at least including the S-bit lower-bit-output-approximate data into a second analog signal; and an analog adder for outputting an added analog signal obtained by adding the first and second analog signals at a predetermined ratio. The S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being .DELTA.L, a minimum step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about .DELTA.L/2.sup.N.

REFERENCES:
patent: 4316178 (1982-02-01), Shibayama et al.
patent: 4340882 (1982-07-01), Maio et al.
patent: 4503421 (1985-03-01), Hareyama et al.
patent: 4523182 (1985-06-01), Harvey et al.
patent: 4740776 (1988-04-01), Sloane
patent: 4843392 (1989-06-01), Gulczynski

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