Digital to analog converter with a weighted capacitive circuit

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

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C341S172000, C341S131000

Reexamination Certificate

active

06906653

ABSTRACT:
D/A converter of this invention including n+1 capacitors in total consisting of one terminating capacitor (C0) and n binary-weighted capacitors (C1-4) that are subjected to binary weighting ratio of 1:2:4: . . . :2(n−1), and, an inverting amplifier (INV1), further comprising: a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1); a switching means for terminating operation (SWR0) supplies one of two main reference voltages (VB,VT) to the terminating capacitor (C0), and then, makes connection of the terminating capacitor (C0) to the output of the inverting amplifier (INV1); a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the n binary-weighted capacitors (C1-4) depending on digital data (D1-4), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1).

REFERENCES:
patent: 5376936 (1994-12-01), Kerth et al.
patent: 5534863 (1996-07-01), Everitt et al.
patent: 5563597 (1996-10-01), McCartney
patent: 6081218 (2000-06-01), Ju et al.
patent: 6259392 (2001-07-01), Choi et al.
patent: 6288669 (2001-09-01), Gata
patent: 6501409 (2002-12-01), Lynn et al.
patent: 0 522 721 (1993-01-01), None
patent: 0 899 884 (1999-03-01), None
patent: 1 353 445 (2003-10-01), None
patent: 3166603 (1997-10-01), None
patent: 09-275345 (1997-10-01), None
Alan B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, 1984, p. 761-764, A Wiley-Interscience Publication, Micro-Linear Corporation, Sunnyvale, California.
Ichiro Fujimori, Akihiko Nogi, Tetsuro Sugimoto, IEEE Journal of Solid-State Circuits, A Multibit Delta-Sigma Audio DAC with 120-dB Dynamic Range, vol., 35, No. 8, Aug. 2000, p. 1066-1073.
Daniel Senderowicz, et al., PCM Telephony: Reduced Architecture for a D/A Converter and Filter Combination, 8107 IEEE Journel of Solid-State Circuits 25 (1990) Aug., No. 4, New York, pp. 987-995.
Y.S. Yee, et al., A Two-Stage Weighted Capacitor Network for D/A-A/D Conversion, IEEE Journel of Solid-State Circuits, vol. SC-14, No. 4, Aug. 1979, pp. 778-781.
Joao C. Vital, et al., A Concurrent Two-Step Flash Analogue-to-Digital Converter Architecture, May 1990.

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