Digital to analog converter using level and timing control...

Details Digital to analog converter using level and timing control... Digital to analog converter using level and timing control...

2000-02-23

2002-04-16

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000, C341S155000

Reexamination Certificate

active

06373417

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for canceling noise in digital to analog converters using level and timing control signals generated by delta sigma modulators.
2. Description of the Prior Art
In digital to analog conversion, it has become typical for delta sigma (or noise shaped) conversion to be used. For a good discussion of the art, see “Delta-Sigma Data Converters” by Norsworthy et al. In prior art, pulse width modulation and delta sigma noise shaping have been advantageously combined. For example, refer to U.S. Pat. No. 5,815,102 by the present inventor, incorporated herein by reference.
FIG. 1
(prior art) shows an oversampling digital to analog converter (DAC), which utilizes a delta sigma converter
114
and a pulse wave modulator (PWM)
116
as the demodulator
112
. The interpolation blocks
104
,
106
,
108
and
110
raise the data rate of the input signal
102
. This reduces the quantization noise introduced by the demodulator. Filter
120
outputs an analog signal. U.S. Pat. Nos. 5,548,286 5,784,017 and 5,708,433 show work by Craven to compensate for the effects by modifying the value of feedback for prior and later samples. This can lead to a good cancellation of the distortion.
FIG. 2
(prior art) shows a second order delta sigma converter which includes correction of one of the feedback paths, for example to correct for distortion introduced in the output data. Input
202
, is added to feedback signal
218
by adder
204
. The signal from adder
204
is fed into first accumulator comprising delay
208
and adder
206
. Adder
210
subtracts feedback
218
and the signal from correction block
220
from the output of the first accumulator and feeds the result into the second accumulator, comprising delay
214
and adder
212
. The output of the second accumulator goes into quantizer
216
. Quantized output
222
also feeds back as feedback signal
218
.
Correction block
220
is shown as a black box which has feedback signal
218
as an input and provides a correction signal. For example, correction block
220
uses signal
218
to lookup a correction factor in ROM and supplies it to adder
210
to be added to feedback signal
218
(both are subtracted from the result of the first accumulator). Equivalently, correction block
220
could have as its output a signal comprising feedback signal
218
added to the correction factor. Then, feedback signal would not itself be an input to adder
210
.
FIG. 3
(prior art) is a block diagram showing demodulator
112
in more detail. High resolution data
302
, for example 12 to 20 bit data, enters delta sigma converter
114
. The sample rate of this data has already been increased from the low rate clock required to code the data, to a medium rate clock used to clock the delta sigma converter. The ratio of the low to the medium clock will typically be a factor of 32 to 1024, for example a low clock of 16 kHz to a medium clock of 1 MHz. Delta sigma modulator
114
is clocked by medium clock
313
, for example at 1 MHz, to generate medium resolution data
306
(2 to 5 bit for example). PWM duty cycle demodulator
116
is clocked by medium clock
313
and high clock
312
. The frequency of the high clock is a multiple of the medium clock, for example 16 MHz. The output of duty cycle demodulator
116
is low resolution data
310
, typically in one or two bit format, at the high clock rate. The optional 0.5 medium clock
314
is used for alternating output data formats. When two different output formats are used in alternating fashion, the 0.5 medium clock rate selects one of the formats for every other data frame output.
A need remains in the art to better cancel noise in digital to analog converters.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide apparatus and methods for canceling noise in digital to analog converters using level and timing control signals generated by delta sigma modulators.
A multiple stage delta sigma converter includes a first delta sigma modulator providing a first modulator output signal, a second delta sigma modulator providing a second output signal, and a format converting block such as a pulse wave modulator for generating a formatted output signal. The level (or width) of the formatted output is dependent upon the first modulator output and the timing (or delay) of the formatted output is dependent upon the second modulator output. The second modulator output is preferably also based upon the first modulator feedback signal. The second modulator quantizer output and feedback signal may be constrained by an output of the first converter. A 1 bit digital to analog converter connected to the output of the PWM converts the formatted output signal to an analog signal.
A delay element may be included between the first modulator and the converter output generating means, and the second modulator output and the second modulator feedback signal constrained by an output of the delay element.
A connecting filter may be included between the first modulator and the second modulator, having as inputs the converter input signal and the first modulator feedback signal, and providing as its output the second modulator input signal.
The connecting filter may comprise a PWM for converting the format of the first modulator feedback signal, step up means for stepping up the frequency of the converter input signal, an adder for combining the output of the PWM and the step up means, an integrator for integrating the output of the adder, a low pass filter for filtering the output of the integrator, and step down means for stepping down the frequency of the output of the low pass filter to form the second modulator input signal.
Alternatively, the connecting filter may comprise a plurality of delays, a plurality of lookup tables, each connected to an input or an output of a lookup table, an adder for combining the outputs of the lookup tables, and an integrator for integrating the output of the adder to form the second converter input signal.


REFERENCES:
patent: 5027119 (1991-06-01), Toyomaki et al.
patent: 5068661 (1991-11-01), Kaneaki et al.
patent: 5124703 (1992-06-01), Kaneaki et al.
patent: 5548286 (1996-08-01), Craven
patent: 5559467 (1996-09-01), Smedley
patent: 5708433 (1998-01-01), Craven
patent: 5784017 (1998-07-01), Craven
patent: 5815102 (1998-09-01), Melanson
Hawksford, M.O.J. “Dynamic Model-Based Linearization of Quantized Pulse-Width Modulation for Applications in Digital-to-Analog Conversion and Digital Power Amplifier Systems,” J. Audio Eng. Soc., vol. 40, No. 4, Apr. 1992, pp. 235-252.
Craven, Peter. “Toward the 24-bit DAC: Novel Noise-Shaping Topologies Incorporating Correction for the Nonlinearity in a PWM Output Stage,” J. Audio Eng. Soc., vol. 41, No. 5, May 1993, pp. 291-313.
Matsuya, Yasuyuli, Kunihara Uchimura, Atsushi Iwata,and Takao Kaneko. “A 17-bit Oversampling D-to-A Conversion Technology Using Multistage Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, pp. 969-975.
Matsya, Yusuyuki, Kuniharu Uchimura, Atsushi Iwata, Tsutomu Kobayashi, Masayuki Ishikawa, and Takeshi Yoshitome. “A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. SC-22, No. 6, Dec. 1987, pp. 921-929.
Candy, James C., and An-ni Huynh. “Double Interpolation for Digital-to-Analog Conversion,” IEEE Transactions on Communications, vol. COM-34, No. 1, Jan. 1986, pp. 77-81.
Carley, Richard L., Richard Schreier, and Gabor C. Temes, “Delta-Sigma ADCs with Multibit Internal Converters.”Delta-Sigma Data Converters: Theory, Design, and Simulation, Ed. Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes, New York: The Institute of Electrical and Electronics Engineers, Inc. pp. 244-281.

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