Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-09-03
2003-11-18
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06650266
ABSTRACT:
FIELD OF THE INVENTION
The present invention may relate to a digital to analog converter (DAC), and to a method of operation of the same. The invention may be especially suitable for implementation in an integrated circuit, but the invention is not limited exclusively to such an implementation.
BACKGROUND TO THE INVENTION
One form of conventional DAC comprises a plurality of switchable (or steerable) current sources coupled to a summing junction, and decoder logic for decoding a digital input signal to control a respective number of the current sources to generate a net current at the summing junction dependent on the digital input signal. A design feature for improving speed performance is that the decoder logic operates asynchronously with respect to the current sources. A clock signal is supplied to the current sources to control sampling of the output of the decoder logic. An extensive clock distribution network is employed to distribute the clock to each of the current cells. Relatively high currents are used to enable high speed clocking and switching of sampling flip-flops. In particular, high currents are used for DAC architectures in which a latch (or flip-flop) is employed within each current source. For example, as the size of a DAC architecture increases (for example from an 8-bit architecture to a 10-bit architecture or to a 12-bit architecture), the number of current sources increases in a power series of 2
x
where x is the number of bits. Each time all of the latches are clocked concurrently, a relatively large current spike is produced. The current spike can cause interference between current sources, and necessitates relatively large smoothing capacitors to smooth a power supply to the DAC. The large smoothing capacitors represent additional cost and size implications. Such a large current demand also means that the power consumption is undesirably high.
A further feature to reduce complexity of the decoder logic is that the decoder logic does not address each and every current source independently. Reduced decoder complexity enables a reduction of the die area for, and power consumption of, the decoder logic. Instead of addressing each current source individually, the decoder logic addresses respective ones of the current sources collectively depending on the value of digital input signal. Addressing collectively has repercussions on testing of a DAC after manufacture, in order to measure or validate a linearity. The linearity depends on uniform matching of the different current sources, and the purpose of the test is to identify matching errors between current sources. The test is performed by measuring the net current produced by plural current sources collectively as the digital input is incremented or decremented progressively over a range of values. In such a situation, the error between current sources becomes progressively masked as the magnitude of the analog output increases. Extremely sensitive, and expensive, measuring equipment is needed to try to detect matching errors. In many cases, accurately measuring the matching error over the entire range of the analogue output is not possible.
SUMMARY OF THE INVENTION
The present invention may relate to a digital to analog converter for converting a digital signal to an analog signal. The digital to analog converter may comprise decoder logic, an array of clocked sub-circuits, a clock generator and a clock signal controller. The decoder logic may be configured to decode the digital signal to a plurality of control signals for controlling generation of the analog signal. The array of clocked sub-circuits may be configured to receive the control signals. The clock generator may be configured to generate a clock signal for clocking the sub-circuits. The clock signal controller may be configured to inhibit application of the clock signal to one or more of the sub-circuits.
Features, objects and advantages of the invention may include: (i) reduction of power consumption; (ii) reduction of interference from the clock distribution network to the current sources; (iii) avoiding or reducing unnecessary clocking of flip flops in the current sources; (iv) an ability to address each current source individually in a test mode; (v) an ability to measure the current from each current source individually; (vi) an ability to detect the matching error equally easily and equally accurately for each current source; (vii) an ability to use inexpensive measuring equipment to measure matching errors and linearity; and/or (viii) an ability to be able to quantify linearity over an entire analog output range of the DAC. Further features, objects and advantages of the invention will become apparent from the following description, claims and drawings.
REFERENCES:
patent: 4481511 (1984-11-01), Hanmura et al.
patent: 4752767 (1988-06-01), Maio et al.
patent: 5084701 (1992-01-01), Sauerwald
patent: 6469947 (2002-10-01), Park
patent: 6509854 (2003-01-01), Morita et al.
Jeanpierre Peguy
LSI Logic Corporation
Sawyer Law Group LLP
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