Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-07-21
2001-08-14
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S148000
Reexamination Certificate
active
06275179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a digital-to-analog converter, and more particularly, the present invention relates to a digital-to-analog converter using a current matrix system.
This application is a counterpart application of Japanese application Serial Number 207480/1998, filed Jul. 23, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A digital-to-analog converter, using a current matrix system, converts inputted digital code to an analog voltage using a plurality of current cells. This device can achieve high conversion rates, and is mainly used for a video field.
FIG. 1
is a circuit diagram showing a conventional digital-to-analog converter.
As shown in
FIG. 1
, a current cell group
1
is made up of plural current cells CP
1
-CPk (k: an integral number, k≧2) connected in a parallel between a power supply voltage VDD and a node A. A current cell CPi (i: any integral number, from 1 to k) flows a current IP when turning on and off in response to individual inputted digital signals CNTPi. The current cell CPi is made up of a circuit so that a constant current PMOS transistor MP
1
connects a switching PMOS transistor MP
2
in series. A gate of the constant current PMOS transistor MP
1
is connected to a node B that is supplied a bias voltage VBP from an external bias circuit. Individual digital signals CNTPi are inputted to a gate of the switching PMOS transistor MP
2
. Further, an output circuit is made up of a resistance R1 located between the node A as an output terminal of an analog output voltage VOUT and a ground potential VSS.
When the individual digital signal CNTPi changes to an L level, the switching PMOS transistor MP
2
turns on and the constant current PMOS transistor MP
1
flows a constant current IP to the resistance R1. When at least one of the plural current cells CP
1
-CPk is selected in response to the individual digital signal CNTPi, a current flows to the resistance R1 as follows:
IP×(the number of selected current cells)
The analog output voltage VOUT has a value as follows:
VOUT=IP× (the number of selected current cells)×R1
In the conventional digital-to-analog converter, it is desirable to increase the amplitude of an analog output voltage and to improve a linear property of an analog output voltage characteristic.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a digital-to-analog converter that can improve the amplitude of the analog output voltage.
According to one aspect of the present invention, for achieving the above object, there is provided a digital-to-analog converter comprising:
a first current cell group which includes a first plurality of current cells for respectively turning on and turning off in response to individually inputted digital signal and which is connected between a first power supply voltage and a first node, wherein the plurality of first current cells are connected in parallel;
a second current cell group which includes a second plurality of current cells for respectively turning on and turning off in response to individually inputted digital signals and opposite the plurality of the first current cells, and which is connected between a second power supply voltage and the first node, wherein the plurality of second current cells are connected in parallel;
an output circuit which converts a current flowing from the first current cell group to the first node, or a current flowing from the first node to the first current cell group, into an analog signal;
wherein each first current cell includes a first conductive type constant current MOS transistor having a gate electrode which is supplied with a first bias voltage from a second node and each second current cell includes a second conductive type constant current MOS transistor having a gate electrode which is supplied with a second bias voltage from a third node.
REFERENCES:
patent: 4683458 (1987-07-01), Hallgren
patent: 5243347 (1993-09-01), Jackson et al.
patent: 5387912 (1995-02-01), Bowers
patent: 5541597 (1996-07-01), Chi-Mao
patent: 5815103 (1998-09-01), Comminges et al.
patent: 6002354 (1999-12-01), Itoh et al.
Cho James H.
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
Tokar Michael
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