Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1998-12-02
2001-05-01
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06225929
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention generally relates to data conversion, and more particularly to digital-to-analog converters for high speed data applications in integrated circuits.
BACKGROUND OF THE INVENTION
A digital-to-analog converter (DAC) converts a digital input signal having N bits to a substantially equivalent analog output signal. Typically, the analog output signal is a voltage signal. There are a number of types of DACs which use a variety of known techniques for converting the digital input signal into an analog voltage output signal. Example types of DACs include charge-scaling DACs, current-scaling DACs, and voltage-scaling DACs. The current-scaling and voltage-scaling DACs are referred to as static designs, while the charge-scaling design is a dynamic design.
In a typical charge-scaling DACs, digital input signal bits control the charging of individual capacitors in a capacitor array to produce an analog voltage output signal, which is based on the total charge of the capacitor array. Typically, the charge-scaling DAC operates by discharging all capacitors in the array during a first clock period. During a non-overlapping second clock period, the capacitors in the capacitor array associated with digital input signal bits at a logic 1 level are connected to a reference voltage, and the capacitors in the capacitor array associated with digital input signal bits at a logic 0 level are connected to ground. The amount of charge from the charged capacitors in the capacitor array associated with digital input signal bits at a logic 1 level is used to obtain the analog voltage output signal.
In one type of current-scaling DAC, a reference voltage is converted into binary-weighted currents. For example, in one such current-scaling DAC, switches couple each input of parallel coupled binary weighted resistors to either a reference voltage or ground depending on if a digital input signal bit is a logic 1 level or a logic 0 level. The outputs of each of the binary weighted resistors are coupled to an output current node. The output current on the output current node is converted to an analog voltage output signal with an operational amplifier.
Another example of a current-scaling DAC employs an R-2R ladder coupled to a reference voltage. Switches are coupled in parallel to outputs of the R-2R resistor ladder. The switches are controlled by digital input signal bits to couple the current from the outputs of the R-2R resistor ladder to ground when the digital input signal bit is at a logic 0 level or to a current output node when the digital input signal bit is at a logic 1 level. The current output on the current output node is converted to an analog voltage output signal with an operational amplifier.
One disadvantage of the current-scaling DAC design is that an additional current-to-voltage converter is required to complete a digital-to-analog conversion. The current-to-voltage converter is typically implemented with a differential operational amplifier and a feedback resistor. The differential operational amplifier has a limited speed based on a settling-time constraints and produces less accurate results due to amplifier offset.
A typical voltage-scaling DAC for converting a N bit digital input signal to a analog voltage output signal employs a series of resistors connected between a reference voltage and ground to selectively produce 2
N
voltages between the reference voltage level and the ground voltage level. The resistor string of the voltage-scaling DAC requires at least 2
N
resistor segments to convert N digital input signal bits. The resistor segments of the resistor string can all be equal values or maybe partial values depending on DAC requirements. The analog voltage output signal is obtained by utilizing at least 2*2
N
switches formed in a multiplexer network and controlled by the N digital input signal bits to select one of the 2
N
voltages produced by the resistor string having the 2
N
resistors between ground and the reference voltage. Although there is no requirement to convert a current to a voltage, a voltage-scaling DAC typically utilizes an operational amplifier to buffer the resistor string from the analog voltage output signal.
The voltage-scaling DAC typically requires that the voltage output of a precision reference is dynamically switched which results in settling-time and accuracy problems. In addition, the at least 2
N
resistors and 2*2
N
switches needed to produce the analog voltage output, occupy a significant area of an integrated circuited incorporating such a voltage-scaling DAC. Moreover, the output impedience of the voltage-scaling DAC is high and difficult to control unless an operational amplifier is used to buffer the output of the resistor string and multiplexer switching network from the analog voltage output signal. If such a operational amplifier is used, the operational amplifier has a limited speed based on a settling-time constraints and produces less accurate results due to amplifier offset.
For reasons stated above and for other reasons presented in greater detail in the Description of the Preferred Embodiments section of the present specification, a static DAC design is desired which produces more accurate results in high speed applications. In addition, there is a need for a static DAC design which occupies a minimal area of an integrated circuit incorporating the DAC design.
SUMMARY OF THE INVENTION
The present invention provides a digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog voltage output signal. Each bit has a first state and a second state. A resistor string includes N resistors serially coupled between a ground node and the analog voltage output signal and includes N nodes (node
1
-node N). Nodes
1
through (N−1) are defined at junctions between the N resistors and node N is coupled to the analog voltage output signal. Each of N switchable current sources provides a current output coupled to a corresponding one of the N nodes of the resistor string. A control gate in each switchable current source receives a corresponding one of the N bits of the digital input signal for controlling each switchable current source to supply current to its corresponding one of the N nodes when its corresponding one of the N bits is in the first state and to not supply current to its corresponding one of the N nodes when its corresponding one of the N bits is in the second state.
In one embodiment, the digital input signal includes M bits in addition to the N bits, wherein each of the M bits has a first state and a second state. The M bits along with the Nth bit, bits N−(N+M), together represent a binary value. In this embodiment, the DAC includes thermometer converting logic for converting bits N−(N+M) into 2
M+1
−1 thermometer code bits representing a thermometer code of the binary value of bits N−(N+M). Each of the 2
M+1
−1 thermometer code bits has a first state and a second state. Each of 2
M+1
−1 switchable current sources provides a current output coupled to node N of the resistor string and includes a control gate for receiving a corresponding one of the 2
M+1
−1 thermometer code bits for controlling each switchable current source to supply current to node N when its corresponding one of the 2
M+1
−1 thermometer code bits is in the first state and to not supply current to node N when its corresponding one of the 2
M+1
−1 thermometer code bits is in the second state.
In one embodiment, the N current outputs from the N switchable current sources are substantially the same. In one such embodiment, a reference current generator provides a reference current. A control circuit receives a reference voltage and controls the reference current based on the reference voltage. Each switchable current source mirrors the reference current such that each current output is substantially equal to the reference current.
One embod
Hewlett--Packard Company
Young Brian
LandOfFree
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