Digital to analog converter having low power consumption

Details Digital to analog converter having low power consumption Digital to analog converter having low power consumption

2001-09-24

2003-10-28

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06639533

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a converter for converting a digital signal to an analog signal, and more particularly, to a digital to analog converter having low power consumption.
2. Description of the Related Art
Digital information can be easily stored in storage medium such as RAM and ROM memories and processed by a personal computer, but numerous electronic devices cannot recognize digital information, such as a television (TV), a camcorder, and a digital camera. The digital information must be converted to an analog signal for processing in these devices.
FIG. 2
is a circuit diagram of an embodiment of a conventional digital to analog converter. Referring to
FIG. 2
, the conventional digital to analog converter includes a reference voltage generator
210
and a conversion current generator
220
.
The reference voltage generator
210
generates voltages Vr
1
and Vr
2
to be used in the conversion current generator
220
, and the conversion current generator
220
comprising a plurality of current cell matrices
221
through
223
generates conversion currents which correspond to digital signals D
0
through DN.
A first current cell matrix
221
includes four MOS transistors M
01
through M
04
and an inverter IN
0
. The two MOS transistors M
01
and M
02
are connected in series from a power supply voltage Vdd and supply current in response to output voltages Vr
1
and Vr
2
of the reference voltage generator
210
. The MOS transistor M
03
driven by the digital signal D
0
discharges the supplied current to a ground voltage GND, or the MOS transistor M
04
driven by an output signal of the inverter IN
0
for inversing the digital signal D
0
supplies the supplied current to an output terminal lo.
A second current cell matrix
222
includes four MOS transistors M
11
through M
14
and an inverter IN
1
. As with the first current cell matrix
221
, the four MOS transistors M
11
through M
14
supply current to the output terminal lo in response to the inverted signal of the digital signal D
1
, or discharges the current to the ground voltage GND in response the digital signal D
1
.
An N+1-th (where N is an integer) current cell matrix
223
includes four MOS transistors MN
1
through MN
4
and an inverter INN. As with the first current cell matrix
221
, the four MOS transistors MN
1
through MN
4
supply current to the output terminal lo in response to the inverted signal of the digital signal DN, or discharge the currents to GND in response to the digital signal DN.
As described above, in conventional digital to analog converters, even if digital signals are deactivated and there is no need for a current source, the current sources supply current continuously. In the conventional digital to analog converter shown in
FIG. 2
, unused current sources supply current continuously to ground GND.
FIG. 3
is another conventional digital to analog converter shown in simplified schematic view. The unused current sources supply current to a closed loop. Thus, in the above conventional circuits, power is unnecessarily wasted in the form of current shunted to ground or in a closed loop.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a digital to analog converter for reducing power consumption.
Accordingly, to achieve the above object, there is provided a digital to analog converter. The digital to analog converter includes a reference bias voltage generator, and a conversion current generator. The reference bias voltage generator generates a predetermined bias voltage using a reference voltage. The conversion current generator comprises a plurality of current generators and supplies currents which correspond to the bias voltage and a plurality of digital signals to an output terminal. The current generators which correspond to activated digital signals of the plurality of digital signals among the plurality of current generators supply the corresponding currents to the output terminal, but the other current generators which correspond to deactivated digital signals of the plurality of digital signals do not supply currents to the output terminal.
It is preferable that each of the plurality of current generators comprises a controller for generating a control signal in response to the bias voltage and at least one signal of the plurality of digital signals, and a current source for supplying currents to the output terminal in response to the control signal.
It is also preferable that the controller comprises a control output terminal for outputting the control signal, an inverter for inverting the digital signal, a first MOS transistor, one end of which is connected to a power supply voltage, the other end of which is connected to the control output terminal, and the gate of which is connected to an output terminal of the inverter, and a second MOS transistor, one end of which is connected to the control output terminal, the other end of which is connected to the bias voltage, and the gate of which is connected to the digital signal.
It is also preferable that one end of the current source is connected to the power supply voltage, the other end of the current source is connected to the output terminal, and the gate of the current source is connected to the control output terminal of the controller.
In order to control the amount of the current supplied to the output terminal, it is preferable that the ratio W/L of the channel width and channel length of each of the third MOS transistors comprising the current source is designed to vary according to a predetermined rule.
According to another aspect of the invention, a digital to analog converter is provided, comprising a bias voltage generator for generating a bias voltage and a current generator having a plurality of current sources for providing current to an output node, each of the current sources being connected to the bias voltage generator and to a corresponding digital activation signal for sourcing current when the digital activation signal is active and not sourcing current when the digital activation signal is inactive. Preferably each of the current sources includes a current sourcing transistor for sourcing current when switched on and at least one biasing transistor for receiving the corresponding digital activation signal, wherein the at least one biasing transistor causes the current sourcing transistor to turn on when the corresponding digital activation signal is active and the current sourcing transistor to turn off when the corresponding digital activation signal is inactive.


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patent: 5706006 (1998-01-01), Hattori
patent: 6104330 (2000-08-01), Redman-White et al.
patent: 6160507 (2000-12-01), Carbou et al.
patent: 6225929 (2001-05-01), Beck
patent: 6236347 (2001-05-01), Cheng
patent: 6268819 (2001-07-01), Fattaruso et al.
patent: 6310568 (2001-10-01), Kurooka
patent: P1996-27359 (1996-07-01), None

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