Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2003-01-13
2004-05-25
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S143000
Reexamination Certificate
active
06741197
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This Application cross-references U.S. patent application Ser. No. 10/256,499 entitled “Cascaded Noise Shaping Circuits with Low Out-of-Band Noise and Methods and Systems Using the Same,” Inventor John L. Melanson, having a filing date of Sep. 27, 2002, which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates in general to digital-to-analog converter (DAC) systems, and, in particular, to digital-to-analog converter (DAC) output stages that accommodate multi-stage noise shaping (MASH) modulators or other such modulators with both data paths and differentiated paths.
2. Background of Invention
Delta-sigma modulators are particularly useful in digital-to-analog converter (DAC) systems. Using oversampling, a delta-sigma modulator spreads the quantization noise power across the oversampling frequency band, which is typically much greater than the input signal bandwidth. Additionally, the delta-sigma modulator performs noise shaping by acting as a highpass filter to the noise; most of the quantization noise power is thereby shifted out of the signal band. A delta-sigma DAC has a digital input summer, a digital interpolation filter, a digital feedback loop, a quantizer, and a DAC output stage at the modulator output. In a first order modulator, the interpolation filter comprises a single integrator stage; the filter in higher order modulators normally includes a cascade of a corresponding number of integrator stages. Higher-order modulators have improved quantization noise transfer characteristics over modulators of lower order, but stability becomes a more critical design factor as the order increases. For a given topology, the quantizer can be either a one-bit or a multiple-bit quantizer.
In cascaded delta-sigma modulator topologies, commonly referred to as MASH (multi-stage noise shaping) modulators, multiple delta-sigma noise shaping loops are cascaded to produce high noise attenuation in the signal band of the modulator noise transfer function (NTF) while maintaining modulator stability. In particular, the typical MASH modulator includes two or more cascaded noise shaping loops, each having a loop filter of a given number of filter stages and a quantizer. The quantized output of one noise shaping loop drives the input of the next noise shaping loop in the cascade such that, except for the first noise shaping loop, the input of each noise shaping loop is the quantization error from the previous noise shaping loop in the cascade. The output of each noise-shaping loop is also passed through error cancellation circuitry that cancels the quantization error from all but the last noise-shaping loop in the cascade. The noise shaping of the quantization error output from the last stage of the cascade is therefore approximately nth-order, where n is the total number of loop filter stages in the cascaded noise shaping loops.
Current state of the art conventional MASH modulator topologies are capable of providing signal band noise attenuation in the NTF on the order of −150 dB. Additionally, MASH modulators are less susceptible to DAC non-linearity in data converter applications and are generally more stable than single-loop modulators, especially when based on low-order, proven-stable individual noise shaping loops. However, conventional MASH modulator topologies also have significant drawbacks. For example, conventional MASH modulator topologies typically achieve high signal band noise attenuation at the expense of increased out-of-band noise gain. More recently, however, out-of-band noise has become a more troublesome problem that must be addressed, especially in such applications as high performance data converters. Consequently, substantial efforts typically must be made. For example, attenuating out-of-band modulator noise at the system level often requires more precise filtering and complicated clocking schemes, which add expense and complexity to the system.
Since the signal from a digital modulator may be low passed filter through switched capacitors (e.g., through a Butterworth filter), a charge transfer buffer is typically utilized at the DAC output stage. The charge transfer buffer receives the switched-capacitor filtered output from the digital modulator. The charge transfer buffer then converts the switched-capacitor filtered output into a continuous time format having relatively low distortion. However, such a charge transfer buffer does not have a differentiated path to accommodate a MASH modulator or other such modulator with both a data path and a differentiated path. A typical charge transfer buffer therefore can only receive signals from a data path, and a MASH modulator cannot utilize the advantages of such a charge transfer buffer.
Therefore, a new type of charge transfer buffer for the DAC output stage is needed to accommodate both the data path and the differentiated path so that a MASH modulator or other such modulator with both data and differentiated paths can utilize such a charge transfer buffer and have the advantages and benefits of such a charge transfer buffer.
SUMMARY OF INVENTION
The principles of the present invention are generally embodied in a digital-to-analog converter (DAC) output stage. A digital-to-analog converter (DAC) output stage has an operational amplifier, an integrating path, a direct or data path, and a differentiated path. The integrating path is coupled in parallel to the operational amplifier. Each of the ends of the integrating path is respectively coupled to an input and an output of the operational amplifier. The direct or data path samples data during a first time sampling phase and is coupled in parallel with the integrating path during a second time sampling phase. The differentiated path is coupled in series with a data input voltage to the input of the operational amplifier.
In one embodiment, the differentiated path is coupled to the input of the operational amplifier during the first time sampling phase. In this embodiment, the differentiated path further includes at least one differentiation capacitor and a second phase switch coupled in series to the at least one differentiation capacitor. The second phase switch is activated during the second sampling time phase and de-activated during the first sampling time phase. In another embodiment, the differentiated path has at least one differentiation capacitor. The DAC output stage further includes a second phase switch coupled between the input of the operational amplifier and one end of the direct path. The second phase switch is activated during the second sampling time phase and de-activated during the first sampling time phase.
The direct path further includes a direct capacitor. The direct path also has one switch coupled in one line with the direct capacitor. The one switch is activated during the first time sampling phase to switchingly couple the direct capacitor in parallel to the operational amplifier. The direct path further has another switch coupled in another line with the direct capacitor. This other switch is activated during the second time sampling phase to switchingly couple the direct capacitor between a ground reference voltage and a digital-to-analog converter element.
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Cirrus Logic Inc.
Lin, Esq. Steven
Williams Howard L.
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