Digital to analog converter array

Details Digital to analog converter array Digital to analog converter array

2002-09-03

2004-04-20

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C345S098000

Reexamination Certificate

active

06724334

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of digital to analog converters, in one embodiment, for optical computing.
BACKGROUND OF THE INVENTION
Optical computing offers advantages over electronic computing for many applications. PCT publications WO 00/72104 and WO 00/72107 describe an optical analog computer which calculates general linear transforms using massively parallel processing. Applications include image compression, image enhancement, pattern recognition, signal identification, signal compression, optical interconnects and crossbar systems, morphologic operations, logical operations, image and signal transformation and modeling neural networks. While it may sometimes be possible, for example in image compression, to use input data that is initially in analog optical form, for many applications the input data is initially stored electronically in digital form, and must be converted into analog optical form before feeding it into the optical computer. To take advantage of the high computation speed of a massively parallel optical computer, there is a need for a system which rapidly converts a large amount of digital data into analog form.
Digital to analog converters (DAC) and analog to digital converters (ADC) are well known. An array of values can be converted from digital to analog form, or from analog to digital form, either in series, feeding each value into a single converter, or in parallel, simultaneously feeding all the values in the array into separate converters. For a very large array, serial conversion can be very slow, and parallel conversion can be very expensive since it requires a large number of converters.
Kleinfelder et al., “A 10 kframe/s 0.18 &mgr;m CMOS Digital Pixel Sensor with Pixel-Level Memory,” 2001 IEEE International Solid-State Circuits Conference, Feb. 5-7, 2001, Session 6.1, CMOS Image Sensors with Embedded Processors, pages 68, 69 and 435, describe a system for parallel analog to digital conversion for a large array of pixels, in which the circuitry needed for each pixel is simpler and less expensive than a complete stand-alone analog to digital converter. A digital ramp signal, consisting of a sequence of 8-bit numbers in numerical order, is generated centrally, together with an analog ramp signal equivalent to the digital ramp signal, i.e. a triangle wave. Both signals are fed to all the pixels. Each pixel has a comparator circuit which compares the analog ramp signal to the value of the analog input for that pixel. When the ramp signal first exceeds the value of the analog input, the comparator circuit activates a digital latching circuit, which latches the current value of the digital ramp signal into the digital memory of that pixel. This digital memory serves as the digital output for the analog to digital conversion.
Albu et al., U.S. Pat. No. 6,320,565, describes a system for digital to analog conversion of a large array of pixels for driving an electro-optic display device, in which all the pixels in one row of the array are converted in parallel, followed by the next row, and continuing until the entire array is converted, then beginning a new frame. A global ramp generator generates an analog ramp signal going from zero to a maximum voltage, which is applied to capacitors associated with all the pixels in the row being processed at that time. An analog to digital converter produces a corresponding global digital ramp signal. For each column in the array, there is a digital comparator which compares the digital ramp signal to an incoming digital video signal for the pixel at the intersection of that column and the row being processed. When the digital ramp signal matches the digital input signal for that column, a sample and hold circuit opens, and isolates the analog ramp signal from the capacitor associated with that pixel, and the voltage on that pixel then remains fixed, decaying slowly until the next frame is processed. In the next ramp cycle, the analog ramp signal is applied to the capacitors associated with the pixels in the next row, and so on. Several ramp cycles before a given row is processed, the analog ramp signal is temporarily reconnected to the capacitors of that row at a time when the analog ramp is close to zero, resetting those pixels to zero. This prevents image artifacts that would occur due to the residual state of the electro-optic material from previous frames.
SUMMARY OF THE INVENTION
An aspect of some embodiments of the invention concerns an array of circuitry for digital to analog conversion in parallel, in which signals for all the pixels of a two-dimensional array of pixels are converted simultaneously, rather than processing only one row of pixels at a time, as in Albu et al. Although this may require more complicated circuitry than Albu et al., for example possibly including a separate digital comparator for each pixel rather only one per column, it is possible to display a frame much more quickly than in the system disclosed by Albu et al. and the circuitry is still simpler and less expensive than a prior art array of circuitry with a stand alone digital to analog converter for each pixel. For the video display application of Albu et al., there would be no advantage to converting all of the pixels of a frame into analog form in parallel, since it is never necessary to display more than a few tens of frame per second, and converting all of the pixels in a frame in parallel would require more expensive hardware than only converting all of the pixels in a row in parallel Even if only one row in the image is updated at a time, at tens of frames per second, it will appear to the human eye as if the entire image is changing continuously. For optical computing, however, it may be useful to convert thousands of frames per second from digital to analog form, for example to avoid having the processor remain idle for a large fraction of the time while the pixels are updated. Thus, for optical computing the cost of the additional hardware may be justified.
The circuitry in accordance with some embodiments of the invention accomplishes the reverse of the task accomplished by the analog to digital conversion array described by Kleinfelder et al. In an exemplary embodiment of the invention, there arc a digital ramp signal and an equivalent analog ramp signal, which are optionally generated centrally, and are accessible to some or all of the elements of the array. In some embodiments of the invention, each element of the array comprises a digital comparator, which compares the digital ramp signal to the input value held in a digital memory associated with that element. When the two values are equal, the comparator generates an enabling signal which activates a sampling and holding circuit associated with that element. The sampling and holding circuit samples the value of the analog ramp signal at that time, and sets the value of an analog output for that element to the value of the analog ramp signal. The analog output is held at this value until the next time the comparator sends the enabling signal to the sampling and holding circuit. The sampling and holding circuit can be quite simple, optionally comprising only a transistor and a capacitor.
Optionally, the output of each pixel in the DAC array is connected directly to the corresponding input pixel of the optical computer, rather than transferring the optical signals along optical fibers. Optionally, the input pixels of the optical computer comprise a multi-quantum well structures made of alternating layers of gallium arsenide (GaAs) and gallium aluminum arsenide (GaAlAs), and the input pixels of the optical computer are bonded to the output pixels of the DAC array using the Flip Chip Bonding technique. Optionally, the DAC array is a monolithic silicon integrated circuit, whose elements are arranged with the same spacing as the input pixels of the optical computer. Unlike in a conventional TV display, the updating of the input pixels need not be done at regular intervals, but optionally is done only when the optical computer re

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