Digital-to-analog-converter

Details Digital-to-analog-converter Digital-to-analog-converter

2003-01-27

2004-02-03

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06686859

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to digital-to-analog converter circuits.
Conventionally, as one of digital-to-analog converter circuits, there is a current output type digital-to-analog converter that is ideally suited for image signal processing.
FIG. 11
is a circuit diagram depicting one example of a current output type digital-to-analog converter circuit formed on a semiconductor chip, where its input digital data is 4 bits.
In
FIG. 11
, the current output type digital-to-analog converter circuit
50
has sixteen current source cells
51
a
-
51
p
disposed at regular intervals. Each of the current source cells
51
a
-
51
p
comprises first and second constant current sources G
1
and G
2
, respectively, that share an output terminal
52
thereof.
Each of the output terminals
52
is electrically connected to first and second analog output lines
54
a
and
54
b
via a changeover switch SW, respectively. Each of the changeover switches SW is electrically connected to a decoder circuit, which is not shown. Each changeover switch SW is designed so that the output terminal
52
is electrically connected to either of a first analog output line
54
a
or a second analog output line
54
b
in accordance with a control signal from the decoder circuit.
The first constant current source G
1
of the respective current source cells
51
a
-
51
p
is connected to a first power supply pad P
1
via a first power supply line L
1
, respectively. The second constant current source G
2
of the respective current source cells
51
a
-
51
p
is also connected to a second power supply pad P
2
via a second power supply line L
2
, respectively. The first and second power supply lines L
1
and L
2
are arranged along the respective current source cells
51
a
-
51
p
in parallel to each other.
On the left-most end of the first power supply line L
1
in
FIG. 11
is formed the first power supply pad P
1
, to which direct-current (DC) voltage Vdd is applied to supply DC voltage to the first constant current source G
1
of the respective current source cells
51
a
-
51
p
. On the right-most end of the second power supply line L
2
in
FIG. 11
is formed the second power supply pad P
2
, to which DC voltage Vdd is also applied to supply DC voltage to the second constant current source G
2
of the respective current source cells
51
a
-
51
p.
The changeover switch SW selected in accordance with the input digital data to the decoder circuit is turned ON or OFF. The currents generated at the first and second constant current sources G
1
and G
2
of the current source cells
51
a
-
51
p
are summed, and the resulting summed output current is output as an analog signal from either of output terminals PO
1
or PO
2
. That is, digital-to-analog conversion is performed.
The value of the current output from each of the current source cells
51
a
-
51
p
is required to be identical. For the output currents from the current source cells
51
a
-
51
p
to be identical, the voltages supplied to the current source cells
51
a
-
51
p
all need to be identical. Thus, the digital-to-analog converter circuit
50
shown in
FIG. 11
is designed to supply DC voltage Vdd, in different directions, to the first and second constant current sources G
1
and G
2
of the current source cells
51
a
-
51
p
via the first and second power supply lines L
1
and L
2
, respectively.
More specifically, line resistances R
1
a
-R
1
p
exist across the first power supply line L
1
, and line resistances R
2
a
-R
2
p
exist across the second power supply line L
2
. It should be appreciated that the line resistances R
1
a
-R
1
p
and R
2
a
-R
2
p
all have the same value. Thus, the first constant current source G
1
of the current source cells
51
a
-
51
p
has an increasingly lower voltage supplied thereto, because the further it is away from the first power supply pad P
1
, the greater the amount of voltage drop. The second constant current source G
2
of the current source cells
51
a
-
51
p
has an increasingly lower voltage supplied thereto, because the further it is away from the second power supply pad P
2
, the greater the amount of voltage drop.
Meanwhile, each of the constant current sources G
1
and G
2
of the current source cells
51
a
-
51
p
is all driven by a common voltage. Thus, the value of the output current output by the current source cells
51
a
-
51
p
is dependent upon a potential difference between the bias supply terminals (not shown) of the constant current sources G
1
and G
2
and the power supply terminals of the constant current sources G
1
and G
2
connected to the first and second power supply lines.
As a result, at each of the current source cells
51
a
-
51
p
, the voltages supplied to the first and second constant current sources G
1
and G
2
and the cell positions are in reverse direction to each other. Accordingly, the output currents of the first and second constant current sources G
1
and G
2
at the respective current cells
51
a
-
51
p
also similarly have reverse current output characteristics depending upon the cell position. It should be appreciated that because the output current at the respective current cell
51
a
-
51
p
is the sum of the currents output from the two constant current sources G
1
and G
2
within that current cell, the output current from the current cell
51
a
-
51
p
remains constant as the effects of the power supply lines L
1
and L
2
cancel each other out.
A method to correct the voltage drops due to the line resistances R
1
a
-R
1
p
and R
2
a
-R
2
p
of the power supply lines L
1
and L
2
to make the values of the output currents output from the current source cells
51
a
-
51
p
identical, is a current output type digital-to-analog converter circuit shown in FIG.
12
. The current output type digital-to-analog converter circuit
60
shown in
FIG. 12
omits the second power supply pad P
2
, so that DC voltage is supplied directly from the first power supply pad P
1
to the first and second power supply lines L
1
and L
2
. In this case, the first power supply pad P
1
is electrically connected to the right-most end of the second power supply line L
2
via a bypass line L
3
. It should be appreciated that the bypass line L
3
has a line resistance R
3
in a similar manner to the first and second power supply lines L
1
and L
2
. Thus, to the second power supply line L
2
is supplied the value of the DC voltage Vdd less the voltage drop due to the line resistance R
3
. In this case, the value of the output currents output from the respective current source cells
51
a
-
51
p
are also similarly made identical.
However, as shown by the characteristic curve X
1
in
FIG. 13
, the amount of voltage drop at each position of the first power supply line L
1
due to the line resistances R
1
a
-R
1
p
actually changes as a quadratic function. Similarly, as shown by the characteristic curve X
2
in
FIG. 13
, the amount of voltage drop at each position of the second power supply line L
2
due to the line resistances R
2
a
-R
2
p
actually changes as a quadratic function.
More specifically, the current value at portions of the first and second power supply lines L
1
and L
2
that are closer to the first and second power supply pads P
1
and P
2
is greater, whereas the current equivalent to one cell of the current source cells
51
a
-
51
p
flows at portions of the first and second power supply lines L
1
and L
2
that are furthest away therefrom. In this way, if the current flowing through the first and second power supply lines L
1
and L
2
increases, the amount of voltage drop developed across the first and second power supply lines L
1
and L
2
having the constant line resistance is an integral value of the voltage drops across the respective line resistances R
1
a
-R
1
p
and R
2
a
-R
2
p
. As a result, the characteristic curves X
1
and X
2
nearly follow the quadratic function.
Thus, at each of the current cells
51
a
-
51
p
, the output current of the first constant current source G
1
has a characteristic as represented by the characte

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