Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-05-14
2004-03-09
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06703957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital-to-analog converter (D/A converter).
2. Prior Art/Related Art
There are many types of D/A converters utilizing PDM and PWM, e.g., delta-sigma D/A converters for voice transmission.
PDM is an abbreviation for pulse-density modulation. In a PDM D/A converter, a data cycle is divided into shorter cycles by means of a higher rate clock. For each clock cycle, an electric potential having either of higher and lower level is output, so that a series of pulses are generated. An input digital bit is represented by the density of the electric potential in one data cycle. The final output analogue signal can be obtained by filtering the series of pulses through an analogue low-pass filter. PDM mechanism is an analogue output mechanism having a characteristic that the output energy has one-to-one relationship with the input data.
Typical PDM mechanism produces a middle level of potential in addition to the binary levels of potential. The period for outputting the middle level of potential is referred to as a reset period. For example, as shown in
FIG. 19
, the potential is +V
ref
(higher level) at the first clock cycle, is decreased to V
center
to indicate a stand-by status at the next clock cycle (reset period), is decreased to −V
ref
(Lower level) at the further next clock cycle, and is increased to V
center
to indicate a stand-by status at the next clock cycle (reset period).
Since one-bit delta sigma D/A converters use the over-sampling technique, they sometimes produce the outputs being similar to that of the PDM mechanisms.
PWM is an abbreviation for pulse-width modulation. In PWM, as shown in
FIG. 20
, a data cycle is divided into shorter clock cycles by means of a higher rate clock as similar to PDM, and an electric potential having either higher or lower level is output for each clock cycle. In contrast to PDM, codes are not represented by the density of potential according to PWM. Rather, the period or the number of clock cycles for outputting the higher level of potential during a data cycle varies according to codes. For example, the first data cycle in
FIG. 20
represents code “one” since the number of clock cycles for outputting the higher level potential is one. The second data cycle in
FIG. 20
represents code “three” since the number of clock cycles for the higher level potential is three.
By virtue of PWM and PDM, the output is limited to have only two or three levels (one among three levels means the reset or stand-by status). Therefore, on the contrary to a multi-valued D/A converter, extraordinarily high accuracy of output can be realized regardless of variation in capabilities of respective elements, and the size of the D/A converter can be minimized.
However, since the potential variation (V
ref
), between which the potential transits, is very large, a large influence occurs due to clock jitters t
j0
as shown in FIG.
21
.
The clock jitters affect the output property considerably. Especially, the deterioration of SNR (signal-to-noise ratio) is a significant problem. In order to solve the problem, it is contemplated that a moving average of the intervals between generations of voltage pulses is calculated for correcting the pulse shapes. Although this method can abate the jitter influences, the discrepancy of capabilities of respective elements may affect the accuracy of the analogue waveform, which is output finally, thereby degrading the essential merits by the binary output from PWM and PDM mechanisms.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a D/A converter utilizing PWM or PDM that can reduce influences of jitters.
According to an aspect of the present invention, a D/A converter comprises a pulse generator for generating PDM pulses in accordance with a digital signal, each of the PDM pulses having a rising stage and a falling stage; and a step former incorporated in the pulse generator for causing at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. With such a structure, noises by jitters may be reduced to enhance the SNR in a D/A converter using PDM.
In an embodiment, the step former may make the stepped shape of the PDM pulse in such a manner that the envelope that is tangent to the stepped shape resembles a sine curve. With such a structure, although a data stream to be transmitted is constituted of alternations of bits “zero” and “one,” the harmonics of the frequency of the alternations can be reduced.
In another embodiment, the step former makes the stepped shape of the PDM pulse in such a manner that the envelope that is tangent to the stepped shape resembles an exponential curve. With such a structure, although the data stream is converted into pulses, the harmonics of the propagation frequency of the pulses can be reduced, thereby lessening influences of the harmonics on the low-pass filter to which the pulses are supplied.
In an embodiment, the step former may include a plurality of delay elements to which the digital signal is supplied, and a plurality of trigger-signal generators for generating trigger signals, which initiate to change an electric potential forming the pulses stepwise, on the basis of the digital signal and the outputs from the delay elements. With such a structure, it is unnecessary to prepare a high rate clock.
According to another aspect of the present invention, a D/A converter comprises a pulse generator for generating PWM pulses in accordance with a digital signal, each of the PWM pulses having a rising stage and a falling stage; and a step former incorporated in the pulse generator for causing at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise. With such a structure, noises by jitters may be reduced to enhance the SNR in a D/A converter using PWM.
In an embodiment, the step former may change an electric potential, which forms the pulses, stepwise at the leading and trailing edges of clock pulses supplied to the digital-to-analog converter. With such a structure, the clock frequency necessary for executing PWM may be reduced, so that it is unnecessary to prepare a high rate clock, and high frequency noises may be reduced. In addition, the number of changes in the potential can be increased in one data cycle.
REFERENCES:
patent: 3543009 (1970-11-01), Voelcker, Jr.
patent: 3836908 (1974-09-01), Hegendorfer
patent: 4868572 (1989-09-01), Reiber
patent: 4947171 (1990-08-01), Pfeifer et al.
patent: 5245345 (1993-09-01), Kohdada et al.
patent: 2000-269761 (2000-09-01), None
patent: 3102024 (2000-10-01), None
patent: 2001-036409 (2001-02-01), None
Kumamoto Toshio
Miki Takahiro
Morimoto Yasuo
Okuda Takashi
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Williams Howard L.
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