Digital-to-analog converter

Details Digital-to-analog converter Digital-to-analog converter

1999-08-18

2001-07-31

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S154000

Reexamination Certificate

active

06268817

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital-to-analog converter, and more particularly, to a digital-to-analog converter which improves reliability of a device.
2. Background of the Related Art
Generally, in a digital-to-analog converter, a resistor string for obtaining analog corresponding to digital has limitation in the number of bits. In other words, to obtain analog corresponding to digital of 10 bits, for example, 2
10
, i.e., 1024 resistors are required. In this case, a resistor string has limitation in the number of bits in view of an occupying area and the like. For this reason, to obtain analog corresponding to digital of K bit more than constant limitation, two stages, i.e., a coarse stage and a fine stage are used. Assuming that K(bit)=M+N, the coarse stage for K(bit) has 2
M
number of resistors and the fine stage for the same has 2
N
number of resistors, wherein M is the number of the most significant bits (MSB) in limitation of the resistor string and N is the number of the other least significant bits (LSB).
When converting digital of K(K=M+N) bit to analog, as shown in
FIG. 1
, a related art digital-to-analog converter includes a coarse stage
11
, a buffer
12
, a fine stage
13
, and an output buffer
14
.
The coarse stage
11
includes 2
M
number of first resistors
15
and first and second select lines
16
and
17
. The first resistors
15
are connected in series between a reference voltage Vref and a ground terminal. The first and second select lines
16
and
17
include a plurality of first and second switch terminals which are alternately connected between the first resistors
15
and the reference voltage, between each of the first resistors
15
and each of the first resistors
15
, and between the first resistors
15
and the ground terminal. The first and second select lines
16
and
17
are controlled by an MSB decoder (not shown).
The buffer
12
includes first and second operational (OP) amplifiers
18
and
19
connected to the first and second select lines
16
and
17
, respectively.
The fine stage
13
includes 2
N
number of second resistors
20
and a third select line
21
. The second resistors
20
are connected in series between output lines of the OP amplifiers
18
and
19
. The third select line
21
includes third switch terminals connected between the second resistors
20
and the first OP amplifier
18
, between each of the second resistors
20
and each of the second resistors
20
, and between the second resistors
20
and the second OP amplifier
19
. The third select line
21
is controlled by an LSB decoder (not shown).
Each of the first resistors
15
and each of the second resistors
20
have the same value as each other.
The output buffer
14
includes a third OP amplifier
22
connected to the third select line
21
.
The operation of the related art digital-to-analog converter will be described below.
The coarse stage
11
has a plurality of voltages of OV to the reference voltage by means of the first resistors
15
. In this state, if a conversion signal for converting digital of K(K=M+N) bit to analog is input to the digital-to-analog converter, the coarse stage
11
selectively turns on the first and second switch terminals of the first and second select lines
16
and
17
, corresponding to the MSB of the input conversion signal in the MSB decoder. The selected value is then output to the buffer
12
.
The outputs of the selected first and second select lines
16
and
17
are input to the first and second OP amplifiers
18
and
19
of the buffer
12
. The output voltages of the first and second OP amplifiers
18
and
19
are output to the fine stage
13
as top and bottom voltages of the fine stage
13
, respectively.
Subsequently, the fine stage
13
has a plurality of voltages within the range of the voltage of the first OP amplifier
18
to the voltage of the second OP amplifier
19
by means of the second resistors
20
. The fine stage
13
selectively turns on the third switch terminals of the third line
21
, corresponding to the LSB of the input conversion signal in the LSB decoder. The selected value is then output to the output buffer
14
.
The output buffer
14
outputs outside an analog signal corresponding to the input digital signal through the third OP amplifier
22
connected to the third select line
21
.
However, the related art digital-to-analog converter has several problems.
Since the output voltage of the coarse stage, which is determined by respectively selecting the first and second select lines by means of the MSB decoder is output as the top and bottom voltages of the fine stage through the first and second OP amplifiers, the top and bottom voltages of the fine stage are varied due to variation of the offset voltage of the OP amplifiers. This results in that error occurs in the fine stage.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a digital-to-analog converter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a digital-to-analog converter in which a resistor connects 2
M
−1 number of first resistors of a coarse stage with a fine stage in series when converting digital of K(K=M+N) bit to analog, so that reliability of a device can be improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a digital-to-analog converter for converting a digital signal of K(K=M+N) bit, in which the number of high bits is M and the number of low bits is N, into an analog signal by a decoder, according to the present invention, includes a coarse stage consisting of first resistor strings having 2
M−1
resistors connected in series with the same size between a reference voltage and a ground terminal, for outputting a first output value corresponding to the M by the decoder, a fine stage formed within the coarse stage between the first resistor strings and the ground terminal to be equivalent to any one of the first resistor strings, for outputting a second output value corresponding to the N by the decoder, a buffer consisting of first and second OP amplifiers which respectively receives the first and second output values, for matching the first and second output values, and an adder for adding outputs of the buffer and outputting an analog signal corresponding to an input digital signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4543560 (1985-09-01), Holloway
patent: 5914682 (1999-06-01), Noguchi
patent: 6133863 (2000-10-01), Peng

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