Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2002-04-30
2003-09-16
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S153000
Reexamination Certificate
active
06621438
ABSTRACT:
FIELD OF THE DISCLOSURE
The present invention relates generally to digital-to-analog converters, and more particularly to non-return to zero digital-to-analog converters.
BACKGROUND
There are at least two major concerns that must be taken into account when designing a digital-to-analog converter (DAC): accuracy and power consumption. The accuracy of a digital-to-analog converter may be expressed in terms of a signal to noise ratio, where inaccuracy is often caused by, among other things, introduction of a noise component, which reduces the signal to noise ratio and makes it difficult to distinguish a desired signal from noise. The noise component in DACs can be greatly affected by the amount of jitter in the output. The greater the jitter, the higher the noise component in the analog signal produced by the DAC. In turn, the higher noise component can lead to decreased accuracy. DACs with large signal to noise ratios are usually sought for modern applications, but achieving such accuracy can be difficult and costly.
In addition to the accuracy of the DAC, power consumption is a particularly important consideration in designing DACs for many popular devices. The less power used by a DAC the better, especially when the DAC is used in a mobile device where excess power consumption can reduce the length of time the device may be used between charging cycles. However, efficient use of power must sometimes be traded for this increased accuracy.
In applications where low power consumption DACs are particularly desirable, non-return to zero (NRTZ) DACs are normally employed because NRTZ DACs have lower peak current requirements than return to zero (RTZ) DACs. One problem with NRTZ DACs, however, is that their accuracy is affected by the pattern of the input bits. For example, an input bit pattern of 0101 causes the output of a NRTZ DAC to change three times, once each clock cycle, so that the DAC produces an output having alternating lows and highs corresponding to the logic zeros and ones of the digital input. However, with an input bit pattern of 0110, the output of an NRTZ DAC changes only twice, once early on when the bit pattern changes from 0 to 1, and then once later when the bit pattern changes from 1 back to 0.
The analog output values can differ based on the number of transitions, because of imperfections in the circuitry of the DAC. For example, real world DACs cannot produce a perfect square wave, nor are the rise and fall times of each square wave exactly equal. Since the value of the analog output is determined by the area under the curves of the square wave, and since the rise and fall times are not equal for each square wave, an input bit pattern of 0101 results in a lower overall output level at low frequency than the output level produced by the bit pattern 0110, when both of these pattern should instead produce the same result.
In order to produce their analog output value, currently available NRTZ DACs generally use differential current addition. Refer to prior art
FIGS. 1 and 2
for examples of current addition.
FIG. 1
represents the use of current addition to generate an output in response to a logic one input, while
FIG. 2
illustrates the use of current addition to generate an output in response to a logic zero input. In
FIG. 1
2
X current sources
10
and
20
are connected continually to outputs
50
and
60
respectively. Current flowing out of output
50
and into output
60
represents a logic one. In order to obtain the
1
X current flowing out of output
50
and into output
60
,
1
X current source
30
is connected to output
50
and
3
X current source
40
is connected to output
60
. The current from current sources
10
and
30
are added together to produce the
1
X current flowing out of output
50
, and the current from current sources
20
and
40
are added together to produce the current flowing into output
60
.
Note that in
FIG. 2
the current flow in outputs
50
and
60
is reversed from the flow shown in FIG.
1
. To achieve this reverse current flow,
1
X current source
30
is connected to output
60
and
3
X current source
40
is connected to output
50
, and the appropriate currents are summed. By switching current sources
30
and
40
appropriately, a logic one or a logic zero digital input can be represented as an analog current at outputs
50
and
60
. Note that in order for current addition to work as illustrated in
FIGS. 1 and 2
,
4
X units of current are needed.
It should be apparent therefore, that a DAC that could achieve greater accuracy than conventional NRTZ digital-to-analog converters and that use less current than those same converters, would be advantageous. If such a DAC also provided less jitter and a correspondingly reduced noise floor, then such a DAC would be even more desirable.
REFERENCES:
patent: 4935740 (1990-06-01), Schouwenhaars et al.
patent: 6061010 (2000-05-01), Adams et al.
patent: 6388598 (2002-05-01), Masuda
patent: 2003/0043062 (2003-03-01), Dedic et al.
A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling, Feb. 5, 1998.
Motorola Inc.
Toler Larson & Abel, LLP
Williams Howard L.
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