Digital-to-analog conversion circuit

Details Digital-to-analog conversion circuit Digital-to-analog conversion circuit

1999-12-22

2002-02-12

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S135000

Reexamination Certificate

active

06346901

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to a digital-to-analog (D/A) conversion circuit using a plurality of current cells.
BACKGROUND OF THE INVENTION
A current output-type digital-to-analog (D/A) conversion circuit is well known in this art. A portion of a typical example of such D/A conversion circuit for 8 bit data is shown in FIG.
2
. The D/A conversion circuit has a matrix arrangement of sixty-three unit current cells
1
, and two weighted current cells (binary cells)
2
and
3
each having a binary weight. Fifteen unit current cells can give an analog output corresponding to four bit data. Thirty-one unit current cells can give an analog output corresponding to five bit data. Sixty-three unit current cells can give an analog output corresponding to 6 bit data. Because the D/A converter further includes the ½ weighted current cell
2
and the ¼ weighted current cell
3
, it can give an analog output corresponding to the 8 bit data. In this matrix arrangement, cells are numbered (0), (1), (2), (3), (4), . . . (16) from left to right.
Each unit current cell
1
includes a unit current source
11
and a selecting switch
12
. The weighted current cells
2
and
3
located at the number (8) each include a weighted current source
21
and
31
respectively and a selecting switch
12
. In
FIG. 2
, such reference numerals are indicated only for the upper and leftmost current source cell (0). The unit and weighted current sources
11
,
21
and
31
on each row are sequentially connected to a power supply terminal
100
in parallel through each of power supply lines
101
-
104
. The selecting switch
12
selectively connects the current sources
11
,
21
and
31
to a lead line
301
or
201
, that is respectively connected to a first and second output terminal
300
and
200
. A decoder (not shown) responds to a digital signal input and controls the switching of the selecting switches
12
in a manner where the decoder switches the selecting switches one by one left to right when the digital signal gradually increases. Each of the first and second output terminals
300
and
200
externally supplies analog output current in a complementary manner. With the D/A conversion circuit so configured, each of the unit and weighted current sources
11
,
21
and
31
is connected to either of the first and second output terminals
300
and
200
according to an input digital code. Thus, a current of the magnitude corresponding to the input digital data flows through the first and second output terminals
300
and
200
, so that D/A conversion is performed.
In more detail of this prior art example, as the most-significant six bits of input digital data increase, the selecting switches
12
of the unit current source cells
1
are sequentially operated to connect each unit current source
11
to either of the first and second output terminals
300
and
200
. Depending on the state of the second least significant bit of the input digital data, the selecting switch
12
of the ½ current source cell
2
is operated to connect the ½ current source
21
to either of the first and second output terminals
300
and
200
. Furthermore, depending on the state of the least significant bit of the input digital data, the selecting switch
12
of the ¼ current source cell
3
is operated to connect the ¼ current source
31
to either of the first and second output terminals
300
and
200
. Thus, a current of magnitude corresponding to the input eight bit digital data flows through the first and second output terminals
300
and
200
, so that 8 bit D/A conversion can be performed.
Rows, or vertical positions, are denoted by alphabets, (a), (b), (c), and (d) as shown in FIG.
2
. Columns, or horizontal positions, are similarly denoted by numerals, (0), (1), (2), (3), (4), and so forth. To identify or address a specific one of the current cells arranged in the matrix form, it is denoted in combination of such row alphabet and column number. For example, a cell located at the lower right corner in the figure is denoted by (d16). To address all the cells in a row or all the cells in a column, they are denoted by using asterisk mark, *, such as (*1) or (a*). Alternately, they may be simply denoted by (1) or (a).
The unit and weighted current cells
1
,
2
,
3
arranged in 4 rows by 16 columns of the prior art current output-type D/A conversion circuit are connected to each other in horizontal direction by the power supply lines
101
-
104
, and further connected to one terminal pad
100
by power supply lines
105
-
108
. The unit current source s
11
and binary current sources
21
and
31
are all driven by a common bias-voltage power supply, and therefore the current value outputted by each of the unit current sources
11
and binary current sources
21
and
31
is dependent upon the power supply voltage applied thereto. Because metal wires of the power supply lines
101
-
108
have significant resistances, the wires can be represented by an equivalent circuit as shown in
FIG. 3
, where wire resistances
400
-
467
exist along the analog power supply lines
101
-
108
. Due to these wire resistances
400
-
467
, a potential distribution occurs in each analog power supply line
101
-
104
such that the potential decreases from current source cell (16) to (0), as shown in FIG.
4
. This potential distribution problem can be solved by selecting the current cells in specific order, that is explained in a co-assigned pending application SC0613AJ.
The unit current cells
1
are generally arranged regularly, while the binary current cells
2
,
3
are located in excess space, in consideration of the characteristics of the semiconductor fabrication process. In
FIG. 3
, the first binary cell
2
is located at (a8), the second binary cell
3
is located at (b8), with no cell being placed at (c8), (d8) or (d0). Accordingly the total current amount of all the current sources on each row (a), (b), (c), (d) is different from each other, and the potential distributions along each analog power supply line
101
-
104
is not identical to each other even if the potential at the right end of each analog power supply line
101
-
104
is assumed to be the same. This potential distribution variation problem has not yet been solved in the prior art.
Thus, the bias conditions for the unit current sources
11
and binary current sources
21
and
31
are varied, and the output current of each of the unit current sources
11
differs depending on the position of its cell, as shown in FIG.
5
. Consequently, the currents supplied externally from the output terminals
300
and
200
do not show precise integer multiples of the unit current source
11
. And the first and second binary current sources
21
and
31
do not give precise ½, ¼ of the unit current. Therefore, a prior art D/A converter suffers a problem that its analog output corresponding to the digital input data is not ideal, resulting in degradation of linearity.
The present invention is intended to alleviate the above potential distribution problem and has its objective to provide a D/A conversion circuit with improved linearity.


REFERENCES:
patent: 4405916 (1983-09-01), Hornak et al.
patent: 5327134 (1994-07-01), Nakamura et al.
patent: 5949362 (1999-09-01), Tesch et al.

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