Digital-to-analog conversion circuit

Details Digital-to-analog conversion circuit Digital-to-analog conversion circuit

2000-04-13

2001-10-30

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S138000

Reexamination Certificate

active

06310568

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a digital-to-analog conversion circuit which generates a current to be input into an ICO (current-controlled oscillator) or the like. More particularly, this invention relates to a digital-to-analog conversion circuit which outputs a current that is non-linear relative to an input digital value.
BACKGROUND OF THE INVENTION
In a PLL (Phase-Locked Loop) circuit utilized in a circuit for reading a magnetic disk or a circuit for receiving a data transmission or the like, an ICO (current-controlled oscillator) is used in many cases for taking out an output signal synchronous with a desired signal. Usually, a digital signal is output from a phase comparator that is a constituent element of the PLL circuit. Therefore, when the ICO is used, it is particularly necessary to provide a digital-to-analog conversion circuit which converts the digital signal output from the phase comparator into an analog control current.
FIG. 5
shows a circuit structure of a conventional digital-to-analog conversion circuit used in the PLL circuit and others. To facilitate the explanation, the digital-to-analog conversion circuit shown in
FIG. 5
has a circuit structure for inputting four-bit digital data. Usually, digital data output from the phase comparator is first stored in registers constituting a buffer, and the ICO converts the data stored in the registers into a current value. Referring to
FIG. 5
, registers
0
to
3
represent bits of four-bit data stored in these registers. The register
3
has a highest-order bit and the register
0
has a lowest-order bit.
The digital-to-analog conversion circuit shown in
FIG. 5
includes inverters G
0
to G
3
which invert the inputs of the registers
0
to
3
respectively. This digital-to-analog conversion circuit also includes twelve MOS transistors and four inverters for taking out a current from a power source voltage Vdd according to signals output from the inverters G
0
to G
3
and for outputting the current taken out as a DAC current (a digital-to-analog current). Particularly, a structure having three MOS transistors and one inverter is allocated to each bit stored in each register.
As shown in
FIG. 5
, a p-channel MOS transistor M
12
with its source connected to the power source voltage Vdd and a p-channel MOS transistor M
13
with its drain connected to a constant current source
9
are connected in series to the register
0
. A p-channel MOS transistor M
11
with its source connected to the power source voltage Vdd and with its drain connected to an output terminal of a DAC current has its gate connected to a connection point between the p-channel MOS transistors M
12
and M
13
, that is, the drain of the p-channel MOS transistor M
12
and the source of the p-channel MOS transistor M
13
.
Then, an output of an inverter G
10
for further inverting the output. of the inverter G
0
is input into the gate of the p-channel MOS transistor M
12
. The output of the inverter G
0
is input into the gate of the p-channel MOS transistor M
13
. In this case, a channel width (hereinafter to be referred to as a W-size) of the p-channel MOS transistor M
11
is set to a.
Based on this structure, when the register
0
has a logic level “L”, the output of the inverter G
0
will have a logic level “H”. This logic level “H” is input into the gate of the p-channel MOS transistor M
13
, to turn OFF the p-channel MOS transistor M
13
. Further, as the output of the inverter G
0
is input into the inverter G
10
, the output of the inverter G
10
will have a logic level “L”. This logic level “L” is input into the gate of the p-channel MOS transistor M
12
, to turn ON the p-channel MOS transistor M
12
. Thus, the potential of the gate of the p-channel MOS transistor M
11
increases, and the p-channel MOS transistor M
11
is turned OFF. Therefore, the electric current is not supplied by the drain of the p-channel MOS transistor M
11
, and accordingly the DAC current does not increase.
On the other hand, when the register
0
has the logic level “H”, the output of the inverter G
0
will have a logic level “L”. This logic level “L” is input into the gate of the p-channel MOS transistor M
13
, to turn ON the p-channel MOS transistor M
13
. Further, the output of the inverter G
10
has the logic level “H”, and this logic level “H” turn OFF the p-channel MOS transistor M
12
. Thus, the potential of the gate of the p-channel MOS transistor M
11
is lowered by the lead-in current of the constant current source
9
, and the p-channel MOS transistor M
11
is turned ON. In other words, a current taken out from the power source voltage Vdd appears in the drain of the p-channel MOS transistor M
11
, and this current is added to the DAC current.
Similarly, a p-channel MOS transistor M
22
having its source connected to the power source voltage Vdd and a p-channel MOS transistor M
23
having its drain connected to a constant current source
9
are connected in series to the register
1
. A p-channel MOS transistor M
21
with its source connected to the power source voltage Vdd and with its drain connected to an output terminal of a DAC current has its gate connected to a node between the p-channel MOS transistors M
22
and M
23
, that is, the drain of the p-channel MOS transistor M
22
and the source of the p-channel MOS transistor M
23
.
Output of an inverter G
20
which inverts the output of the inverter G
1
is input into the gate of the p-channel MOS transistor M
22
. The output of the inverter G
1
is input into the gate of the p-channel MOS transistor M
23
. The W-size of the p-channel MOS transistor M
21
is set to two times the W-size of the p-channel MOS transistor M
11
, that is a×2. Since the drain current of the MOS transistor is directly proportional to the W-size, the drain current of the p-channel MOS transistor M
21
, that is the current that can be added to the DAC current, becomes two times the drain current of the p-channel MOS transistor M
11
.
With such a constitution, when the register
1
has the logic level “L”, the output of the inverter G
1
will have a logic level “H”. This logic level “H” turns OFF the p-channel MOS transistor M
23
. As the output of the inverter G
1
is input into the inverter G
20
, the output of the inverter G
20
will have a logic level “L”. This logic level “L” turns ON the p-channel MOS transistor M
22
. Thus, the gate potential of the p-channel MOS transistor M
21
is increased, and the p-channel MOS transistor M
21
is turned OFF. Therefore, the electric current is not supplied by the drain of the p-channel MOS transistor M
21
, and accordingly the DAC current does not increase.
On the other hand, when the register
0
has the logic level “H”, the output of the inverter G
1
will have a logic level “L”. This logic level “L” turns ON the p-channel MOS transistor M
23
. Further, the output of the inverter G
20
has the logic level “H”, and this logic level “H” turns OFF the p-channel MOS transistor M
22
. Thus, the potential of the gate of the p-channel MOS transistor M
21
is lowered by the lead-in current of the constant current source S, and the p-channel MOS transistor M
21
is turned ON. In other words, a current taken out from the power source voltage Vdd appears in the drain of the p-channel MOS transistor M
21
, and this current is added to the DAC current.
The register
2
and the register
3
also have structures and operations similar to those described above, and their explanation will be omitted. However, in
FIG. 5
, of the structure corresponding to the register
2
, the W-size of a p-channel MOS transistor M
31
is four times the W-size of the p-channel MOS transistor M
11
, that is a×4. Further, of the structure corresponding to the register
3
, the W-size of a p-channel MOS transistor M
41
is eight times the W-size of the p-channel MOS transistor M
11
, that is a×8. Accordingly, the drain currents of the p-channel MOS transistors M
31
and M
41
also are four times and eight times of the drain current of the p-channel MOS transistor M
11

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