Digital timing recovery operable at very low or less than...

Details Digital timing recovery operable at very low or less than... Digital timing recovery operable at very low or less than...

2004-07-09

2009-02-03

Tran, Khanh C (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S355000

Reexamination Certificate

active

07486747

ABSTRACT:
A receiver (20) for performing timing recovery over at least one complex channel at low or less than zero SNR (signal power to noise power, in dB) has at least one receive element such as an antenna, an analog-to-digital converter21(ADC), a fractional interpolation filter23, a matched filter24, and a timing correction loop26. The timing correction loop26selects a minimum mean square error from the output of the matched filter24to determine a timing signal output to the interpolation filter23, and provides one-bit weights to the matched filter24. Preferably, the timing correction loop26includes a magnitude detector26c, a moving average filter26b, and a timing error detector26athat outputs an integer m and fractional μ timing factor to the interpolation filter23. Within a phase correction loop27is a maximum likelihood channel estimator27band a phase error detector27athat controls a phase rotator22disposed between the ADC21and the interpolation filter23.

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