Digital timing recovery method and apparatus for a coded data ch

Details Digital timing recovery method and apparatus for a coded data ch Digital timing recovery method and apparatus for a coded data ch

1994-09-27

1996-09-24

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

H04L 700

Patent

active

055598404

ABSTRACT:
A digital timing recovery circuit for rapid acquisition and synchronization of sampling clock phase in a data playback signal processing channel. The filtered playback signal in a (1,7)ML coded playback channel is sampled at the rate of one sample per bit window and the digitized sample values are processed with a (1,7)ML decoding procedure to produce decoded bits. A digital timing recovery circuit of this invention uses the digitized sample values directly to control the sampling clock phase by computing a digital phase error signal (PES) that is a constant function of phase error independent of data pattern. The PES depends only on the adjacent samples before and after a peak signal value. These "side-samples" contain maximal timing information because they occur at the steepest slope of the read-back signal and are thus most sensitive to clock phase error. Both side-samples of every pulse are weighted uniformly, independent of data pattern, thereby maximizing available phase information and ensuring the rapid acquisition and convergence of the sampling clock phase.

REFERENCES:
patent: 4945538 (1990-07-01), Patel
patent: 5266850 (1993-11-01), Au et al.
patent: 5267267 (1993-11-01), Kazawa et al.
patent: 5276711 (1994-01-01), Rossi
patent: 5282216 (1994-01-01), Patel et al.
patent: 5291500 (1994-03-01), Patel et al.
patent: 5295128 (1994-03-01), Hutchins et al.

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