Registers – Platform operated – Platform actuated traffic counters
Patent
1975-05-05
1976-07-27
Zache, Raulfe B.
Registers
Platform operated
Platform actuated traffic counters
179 15BS, 3401725, 235 92EC, 235 92DP, 235 92R, H03K 2100
Patent
active
039719200
ABSTRACT:
A digital storage system provides an economical means by which binary data words describing a series of events occurring randomly in time can be stored during a recording period and later retrieved in their sequence of occurrence with the time-of-event information preserved. A first recirculating shift register memory having arbitrarily great length, such as 4096 cells, each cell capable of storing a parallel binary data word such as 6 (or N bits), a second recirculating shift register memory of equal length, similarly capable of storing parallel binary error codes, and a cell counter having a counting capacity equal to the numerical length of said shift register memories are clocked in synchronism and comprise the storage medium. A clock control circuit provides shift clock pulses to said shift register memories and cell counter at basic clock intervals such as 16 microseconds during data absence, but alternatively provides a "premature" shift clock pulse when a "data ready" flag appears, causing the entry of a data word into said first shift register memory. An error encoder circuit provides a binary count of sub-intervals of the basic clock interval, such as zero through fifteen microseconds (vernier time count), and provides a binary count of the excess of shift clock pulses over basic clock intervals (borrowed time count) when data words arrive at a rate higher than the basic clock rate, up to a maximum excess such as 15 units, each equivalent to one "prematurely" clocked cell. Said vernier time count and borrowed time count comprise an error code which is supplied to said second shift register memory and entered into storage simultaneously with the entry of each data word. An event time correction circuit provides time-of-event information during data retrieval, arithmetically combining the vernier time and borrowed time error code supplied by said second shift register memory with the event storage location number which represents approximate time-of-event and is supplied by said cell counter. The retrieved data thus appears as a column of simultaneous bits consisting of the descriptive data word(s) and the time of event.
REFERENCES:
patent: 3573742 (1971-04-01), Riddell
patent: 3708690 (1973-01-01), Paivinen
patent: 3778778 (1973-12-01), Ragen
patent: 3862373 (1975-01-01), Cohen et al.
patent: 3867579 (1975-02-01), Colton et al.
patent: 3887769 (1975-06-01), Cichetti, Jr.
patent: 3896417 (1975-07-01), Beecham
Smith Robert C.
The Bendix Corporation
Thornton William F.
Vandenburg John P.
Zache Raulfe B.
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