Digital threshold detector with hysteresis

Details Digital threshold detector with hysteresis Digital threshold detector with hysteresis

1985-10-25

1987-10-13

Griffin, Robert L.

Pulse or digital communications

Repeaters

Testing

307359, H04L 2506, H04L 2510

Patent

active

047003650

ABSTRACT:
As the 8-bit input signal applied to a threshold device reaches a first threshold level, the 1-bit output signal changes from a logical zero to a logical one. The 1-bit output signal is delayed by one system clock period and fed back. The delayed 1-bit output signal is combined (e.g., merged or added) with the 8-bit input signal, and the resulting signal is applied to the threshold device to provide a hysteresis feature. Once the delayed 1-bit output signal becomes a logical one, the input signal has to drop below a second, lower threshold level before the 1-bit output signal can revert back to a logical zero, whereby a margin of noise immunity is provided.

REFERENCES:
patent: 3758868 (1973-09-01), Brown
patent: 3784921 (1974-01-01), Iadipaolo
patent: 3828204 (1984-08-01), Farnsworth
patent: 4007382 (1977-02-01), Warberg
patent: 4100532 (1978-07-01), Farnbach
patent: 4291355 (1981-09-01), Dinger
patent: 4326168 (1982-04-01), Acker
patent: 4387465 (1984-02-01), Dolikian
patent: 4387465 (1983-06-01), Becker
patent: 4407020 (1983-09-01), Helliwell et al.
patent: 4525638 (1985-06-01), Gray
patent: 4602374 (1986-07-01), Nakamura et al.

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