Digital test and maintenance architecture

Details Digital test and maintenance architecture Digital test and maintenance architecture

1994-01-19

1997-02-04

Beausoliel, Jr., Robert W.

G06F 1126

Patent

active

056007884

ABSTRACT:
A testing device has an architecture including a board test interface for coupling to test points on a circuit board; a programmable processor, coupled to the board test interface, for controlling a test of the circuit board via the board test interface; and a first communications interface, coupled to the programmable processor, for coupling to a like first communications interface located on another testing device. The programmable processor uses the first communications interface for communicating test commands and test results with the other testing device, so that a complete test of a system can be produced. The testing device may further include a control port, coupled to the programmable processor, for communicating system test commands between a host processor and the programmable processor. In response to a first system test command received from the host processor via the control port, the programmable processor may use the first communications interface to send a second test command to another testing device. Also, a number of identical testing devices, each located on a corresponding one of a number of circuit boards in a system, may use the first communications interface to transmit test results to one of the testing devices, designated as a master coordinating device. The master coordinating device then forwards all of the test results to a host processor for analysis. The entire testing device may be fabricated as a single integrated circuit, in order to provide great testability without occupying a great deal of circuit board space.

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