Digital television transmitter and method of coding data in...

Television – Receiver circuitry

Reexamination Certificate

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C348S726000

Reexamination Certificate

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08054385

ABSTRACT:
A pre-processor pre-processes enhanced data packets by coding the enhanced data packets for forward error correction (FEC) and expanding the FEC-coded data packets. A data formatter adds first null data into first place holders within each pre-processed enhanced data packet. A first multiplexer multiplexes the main data packets with the enhanced data packets having the first null data. A holder inserter inserts second null data into second place holders within an enhanced data packet outputted from the first multiplexer. A data interleaver replaces the second null data with parity data. A data generator generates at least one known data sequence. A symbol processor replaces the first null data included in an output of the data interleaver with the known data sequence(s). A non-systematic RS encoder generates the parity data by performing non-systematic RS-coding on an output of the symbol processor, and provides the parity data to the data interleaver.

REFERENCES:
patent: 7167212 (2007-01-01), Choi et al.
patent: 2002/0036714 (2002-03-01), Markman
patent: 2003/0152107 (2003-08-01), Pekonen
patent: 2004/0090997 (2004-05-01), Choi et al.
patent: 2007/0076829 (2007-04-01), Choi et al.
patent: 1386017 (2002-12-01), None
patent: 1386018 (2002-12-01), None
patent: 1582580 (2005-02-01), None
patent: 1020030026236 (2003-03-01), None
patent: PA03005163 (2003-09-01), None
patent: PA04002568 (2004-12-01), None
patent: 03/003747 (2003-01-01), None
patent: 2004-107619 (2004-12-01), None
Advanced Television Systems Committee (ATSC), “ATSC Standard: Digital Television Standard (A/53), Revision D, Including Amendment No. 1,” Jul. 27, 2005.

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