Multiplex communications – Wide area network – Packet switching
Patent
1984-05-30
1986-03-11
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
H04Q 1104
Patent
active
045758441
ABSTRACT:
A hierarchical message channel storage of a digital switching system which is connected to time division multiplex transmission lines includes at least a small-capacity high-speed memory and a large-capacity low-speed memory. A control section performs switching using the high-speed memory when a circuit switching call is received. However, when a packet switching call is received, the control section accesses the high-speed memory to temporarily store transmission data in the high-speed memory and performs switching for one of the output transmission lines or the control section accesses the high- and low-speed memories to temporarily store data in the low-speed memory through said high-speed memory so as to perform switching for one of said output transmission lines. In this case, the access cycles of the high-speed memory have circuit/packet switching call cycles and switching program cycles. A single storage is commonly used for the circuit switching call requiring writing data at a high speed, the packet switching call requiring storing a great amount of data, and the switching program.
REFERENCES:
patent: 3732548 (1973-05-01), Howells et al.
patent: 3988545 (1976-10-01), Kuemmerle et al.
patent: 4413337 (1983-11-01), Dauphin et al.
patent: 4494231 (1985-01-01), Slawy et al.
Review of the Electrical Communication Laboratories, vol. 28, Numbers 5-6, May-Jun., pp. 328-337, published by Musashino Electrical Communication Laboratory of Nippon Telegraph & Telephone Public Corporation.
Naecon 1981; Proceedings of the IEEE; "A Distributed Processing Architecture for Voice/Data Switching"; Ross et al.; May 19-21, 1981; pp. 350-6 to 356.
Kosuge Yasuharu
Miyaho Noriharu
Nippon Telegraph & Telephone
Olms Douglas W.
Scutch III Frank M.
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